SYNCHRONOUS ETHERNET WAN PLL Product Brief and Clock Generation for IEEE-1588 IDT82V3398 Provides IN1~IN6 input clocks whose frequencies cover from 1 Hz FEATURES (1PPS) to 625 MHz HIGHLIGHTS 1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25 Single PLL chip: MHz, 6.48MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 Features 0.5 mHz to 560 Hz bandwidth MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz or 156.25 Provides node clock for ITU-T G.8261/G.8262 Synchronous MHz for CMOS inputs Ethernet (SyncE) 1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25 Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) MHz, 6.48 MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 jitter generation requirements MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz, 156.25 Provides node clocks for Cellular and WLL base-station (GSM MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz for dif- and 3G networks) ferential inputs Provides clocks for DSL access concentrators (DSLAM), espe- Internal DCO can be controlled by an external processor to be used cially for Japan TCM-ISDN network timing based ADSL equip- for IEEE-1588 clock generation ments Supports Forced or Automatic operating mode switch controlled by Provides clocks for 1 Gigabit and 10 Gigabit Ethernet application an internal state machine. It supports Free- Run, Locked and Hold- It supports clock generation for IEEE-1588 applications over modes Supports manual and automatic selected input clock switch MAIN FEATURES Supports automatic hitless selected input clock switch on clock fail- Provides an integrated single-chip solution for Synchronous Equip- ure ment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option Provides a 2 kHz, 4 kHz, 8 kHz, or 1PPS frame sync input signal, 1 and EEC-Option 2 Clocks and a 2 kHz, 8 kHz, or 1PPS frame sync output signals Provides SONET clocks with less than 1.5 ps of RMS Phase Jitter Provides output clocks for BITS, GPS, 3G, GSM, etc. (12 KHz - 20 MHz) Supports PECL/LVDS and CMOS input/output technologies Supports 1 pps input and output Supports master clock calibration Employs PLL architecture to feature excellent jitter performance Supports Master/Slave application (two chips used together) to and minimize the number of the external components enable system protection against single chip failure Supports programmable DPLL bandwidth from 0.5 mHz to 560 Hz Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, -5 -8 Supports 1.1X10 ppm absolute holdover accuracy and 4.4X10 ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom- ppm instantaneous holdover accuracy mendations Supports hitless reference switching to minimize phase transients OTHER FEATURES on the DPLL output to be no more than 0.61 ns I2C and Serial microprocessor interface modes Supports programmable input-to-output phase offset adjustment IEEE 1149.1 JTAG Boundary Scan Limits the phase and frequency offset of the outputs Single 3.3 V operation with 5 V tolerant CMOS I/Os Provides OUT1~OUT6 output clocks whose frequencies cover from 72-pin QFN package, Green package options available 1 Hz (1PPS) to 644.53125 MHz 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0 APPLICATIONS MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 1 Gigabit Ethernet and 10 Gigabit Ethernet 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, BITS / SSU 25MHz, 25.78125 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz SMC / SEC (SONET / SDH) or 156.25 MHz or 161.1328125 MHz for CMOS outputs DWDM cross-connect and transmission equipments 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0 Synchronous Ethernet equipments MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, Central Office Timing Source and Distribution 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, Core and access IP switches / routers 77.76 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz, 156.25 Gigabit and Terabit IP switches / routers MHz, 161.1328125 MHz, 311.04 MHz, 312.5 MHz, 322.265625 IP and ATM core switches and access equipments MHz, 622.08 MHz, 625 MHz or 644.53125 MHz for differential Cellular and WLL base-station node clocks Outputs Broadband and multi-service access equipments 1 August 1, 2012 DSC-7238/-IDT82V3398 PRODUCT BRIEF SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 DESCRIPTION The IDT82V3398 is an integrated, single-chip solution for the Syn- The device provides programmable DPLL bandwidths: 0.5 mHz to chronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EEC- 560 Hz. Different settings cover all SONET / SDH clock synchronization Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet requirements. equipment, DWDM and Wireless base station. A highly stable input is required for the master clock in different appli- The device consists of a highly quality and configurable DPLL to pro- cations. The master clock is used as a reference clock for all the internal vide system clock for node timing synchronization within a SONET / circuits in the device. It can be calibrated within 741 ppm. SDH / Synchronous Ethernet network. All the read/write registers are accessed through a microprocessor An input clock is automatically or manually selected for the DPLL. interface. The device supports I2C and serial microprocessor interface The DPLL has three primary operating modes: Free-Run, Locked and modes. Holdover. In Free-Run mode, the DPLL refers to the master clock. In In general, the device can be used in Master/Slave application. In Locked mode, the DPLL locks to the selected input clock. In Holdover this application, two devices should be used together to enable system mode, the DPLL resorts to the frequency data acquired in Locked mode. protection against single chip failure. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process varia- tions. There is also a high performance APLL that is used for low jitter SONET and Ethernet Clocks Description 2 August 1, 2012