Synchronization Management WAN PLL and 82V3399 Clock Generatiion for IEEE-1588 SHORT FORM DATA SHEET This short form datasheet is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on the last page. Provides IN1~IN6 input clocks whose frequencies cover from 1 Hz FEATURES (1PPS) to 625 MHz HIGHLIGHTS Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS inputs Single chip PLL: Includes 25 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for dif- Features 0.5 mHz to 560 Hz bandwidth ferential inputs Provides node clock for ITU-T G.8261/G.8262 Synchronous Internal DCO can be controlled by an external processor to be used Ethernet (SyncE) for IEEE-1588 clock generation Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) Supports Forced or Automatic operating mode switch controlled by jitter generation requirements an internal state machine. It supports Free- Run, Locked and Hold- Provides node clocks for Cellular and WLL base-station (GSM over modes and 3G networks) Supports manual and automatic selected input clock switch Provides clocks for DSL access concentrators (DSLAM), espe- Supports automatic hitless selected input clock switch on clock fail- cially for Japan TCM-ISDN network timing based ADSL equip- ure ments Supports three types of input clock sources: recovered clock from Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applica- STM-N or OC-n, PDH network synchronization timing and external tions synchronization reference timing It supports clock generation for IEEE-1588 application Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 kHz or 8 kHz frame sync output signal MAIN FEATURES Provides a 1PPS sync input signal and a 1PPS sync output signal Provides an integrated single-chip solution for Synchronous Equip- Provides output clocks for BITS, GPS, 3G, GSM, etc. ment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option Supports PECL/LVDS and CMOS input/output technologies 1 and EEC-Option 2 Clocks Supports master clock calibration Provides SONET clocks with less than 1 ps of RMS Phase Jitter Supports Master/Slave application (two chips used together) to (12 kHz - 20 MHz) enable system protection against single chip failure Supports 1PPS input and output Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, Employs PLL architecture to feature excellent jitter performance ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 recom- and minimize the number of the external components mendations Integrates T0 DPLL and T4 DPLL T4 DPLL locks independently or locks to T0 DPLL OTHER FEATURES Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 I2C and Serial microprocessor interface modes steps) and damping factor (1.2 to 20 in 5 steps) IEEE 1149.1 JTAG Boundary Scan -5 -8 Single 3.3 V operation with 5 V tolerant CMOS I/Os Supports 1.1X10 ppm absolute holdover accuracy and 4.4X10 72-pin QFN package, green package options available ppm instantaneous holdover accuracy Supports hitless reference switching to minimize phase transients APPLICATIONS on T0 DPLL output to be no more than 0.61 ns 1 Gigabit Ethernet and 10 Gigabit Ethernet Supports programmable input-to-output phase offset adjustment BITS / SSU Limits the phase and frequency offset of the outputs SMC / SEC (SONET / SDH) Provides OUT1~OUT6 output clocks whose frequencies cover from DWDM cross-connect and transmission equipment 1 Hz (1PPS) to 644.53125 MHz Synchronous Ethernet equipment Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS outputs Central Office Timing Source and Distribution Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, for Core and access IP switches / routers CMOS outputs Gigabit and terabit IP switches / routers Includes 25 MHz,125 MHz, 156.25 MHz, 312.5 MHz and 625 IP and ATM core switches and access equipment MHz for differential outputs Cellular and WLL base-station node clocks Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, Broadband and multi-service access equipment 322.265625 MHz and 644.53125 MHz for differential outputs 82V3399 REVISION 9 01/05/16 9 2016 Integrated Device Technology, Inc.82V3399 SHORT FORM DATA SHEET DESCRIPTION The 82V3399 is an integrated, single-chip solution for the Synchro- acquired in Locked mode. Whatever the operating mode is, the DPLL nous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EEC- gives a stable performance without being affected by operating condi- Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet tions or silicon process variations. equipment, DWDM and Wireless base station. There are 2 high performance APLLs that can be used for low jitter The device supports several types of input clock sources: recovered SONET and Ethernet Clocks clock from Synchronous Ethernet, STM-N or OC-n, PDH network syn- The device provides programmable DPLL bandwidths: 0.5 mHz to chronization timing and external synchronization reference timing. 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different The device consists of T0 and T4 paths. The T0 path is a high quality settings cover all SONET / SDH clock synchronization requirements. and highly configurable path to provide system clock for node timing A highly stable input is required for the master clock in different appli- synchronization within a SONET / SDH / Synchronous Ethernet network. cations. The master clock is used as a reference clock for all the internal The T4 path is simpler and less configurable for equipment synchroniza- circuits in the device. It can be calibrated within 741 ppm. tion. The T4 path locks independently from the T0 path or locks to the T0 All the read/write registers are accessed through a microprocessor path. interface. The device supports I2C and serial microprocessor interface An input clock is automatically or manually selected for T0 and T4 modes. path. Both the T0 and T4 paths support three primary operating modes: In general, the device can be used in Master/Slave application. In Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to this application, two devices should be used together to enable system the master clock. In Locked mode, the DPLL locks to the selected input protection against single chip failure. clock. In Holdover mode, the DPLL resorts to the frequency data SYNCHRONIZATION MANAGEMENT WAN PLL AND 10 REVISION 9 01/05/16 CLOCK GENERATIION FOR IEEE-1588