2 I C Programmable Ethernet Clock 8T49N4811 Generator DATA SHEET General Description Features The 8T49N4811 is a highly flexible FemtoClock NG Fourth generation FemtoClock NG technology pin-programmable clock generator suitable for networking and Generates multiple copies of 25MHz, 50MHz, 100MHz, 125MHz, communications applications. It is able to generate five different 156.25MHz or 312.5MHz output frequencies with multiple copies of each. A fundamental mode Typical input frequency is 25MHz, with optional 125MHz and crystal, single-ended, or differential input reference may be used as 156.25MHz input support the source for the output frequency. Differential outputs are pin programmable for LVDS or LVPECL The use of pin-programming to select the input source / frequency, RMS phase jitter at 156.25MHz: <300fs typical desired output frequencies and output styles allow a single device to Power Supply Rejection Ratio better than -50dBc from be used in a wide variety of applications without the need for register 10k-1.5MHz at 3.3V power supply programming. Full 3.3V and 2.5V Supply Voltages Selection pins use 3-level options to maximize flexibility while -40C to +85C ambient operating temperature minimizing package size. Selection is performed by tying a selection pin high or low or by leaving it floating, eliminating the need for 56-pin VFQFPN, lead-free (RoHS 6) packaging passive components to drive a desired logic level. Block Diagram 2.5V 5% or 3.3V 10% PLL Bypass SDATA, SCLK LVPECL/LVDS Bank A 1 /A 0 125MHz/156.25MHz/312.5MHz 1 IIC ADRX SEL LVPECL/LVDS Bank B 6 IN SEL /B 0 50MHz/125MHz/156.25MHz 1 XTAL IN f XTAL OUT OSC IN 0 LVPECL/LVDS Bank C 2 f IN APLL /C 0 100MHz/125MHz/156.25MHz 1 DIN 1 100 LVPECL/LVDS Bank D0 1 nDIN /D0 25MHz/125MHz/156.25MHz SLEW LVCMOS Input Divider LVCMOS CTRL Frequency, 3 Output Type, LVCMOS Bank D1 1 Qx CTRL Slew Rate, & 25MHz/125MHz /D1 QB CTRL 1:0 Output Enable Frequency Select Control INPUT DIVSEL 4 Output Enable,Type, & Slew Rate Control DIVSEL x 8T49N4811 REVISION B 11/12/15 1 2015 Integrated Device Technology, Inc.8T49N4811 DATA SHEET Pin Assignment 42 41 40 39 38 37 36 35 34 33 32 313029 QB CTRL0 43 28 SLEW LVCMOS V 44 27 V DD DD QA CTRL 45 26 QB CTRL1 8T49N4811 V 46 25 V DD OA DD OD 56-Lead VFQFN nQA0 47 24 QD0 QA0 48 23 nQD0 8mm x 8mm x 0.90mm DIVSEL A 49 22 QD CTRL Package Body QC CTRL 50 21 V 5.9mm x 5.9mm ePad Size DD ODS V 51 20 QD0 S DD OC NLG Suffix nQC1 52 19 nc Top View QC1 53 18 DIVSEL B nQC0 54 17 Reserved QC0 55 16 SDATA V 56 15 SCLK DD OC 12 3 4567 89 10 11 12 13 14 2 I C PROGRAMMABLE ETHERNET CLOCK GENERATOR 2 REVISION B 11/12/15 DIVSEL C QB0 V nQB0 DD IN SEL QB1 DIN nQB1 nDIN V DD OB V QB2 DD XTAL XTAL IN nQB2 XTAL OUT QB3 PLL BYPASS nQB3 IIC ADRX SEL V DD OB V QB4 DDA INPUT DIVSEL nQB4 DIVSEL D0 QB5 LVCMOS CTRL nQB5