2.5 V Differential LVDS Clock Divider 8T74S208C-01 and Fanout Buffer Datasheet General Description Features The 8T74S208C-01 is a high-performance differential LVDS clock One differential input reference clock divider and fanout buffer. The device is designed for the frequency Differential pair can accept the following differential input levels: division and signal fanout of high-frequency, low phase-noise clocks. LVDS, LVPECL, CML The 8T74S208C-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew Integrated input termination resistors characteristics make the 8T74S208C-01 ideal for those clock Eight LVDS outputs distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make Selectable clock frequency division of 1, 2, 4 and 8 interfacing to the reference source easy and reduce passive Maximum input clock frequency: 1GHz component count. Each output can be individually enabled or 2 disabled in the high-impedance state controlled by a I C register. On LVCMOS interface levels for the control inputs power-up, all outputs are disabled. 2 Individual output enabled/ disabled by I C interface Output skew: 45ps (maximum) Output rise/fall times: 370ps (maximum) Low additive phase jitter, RMS: 96fs (typical) Full 2.5V supply voltage Outputs disabled at power-up Lead-free (RoHS 6) 32-Lead VFQFN packaging -40C to 85C ambient operating temperature Block Diagram Pin Assignment Q0 nQ0 32 31 30 29 28 27 26 25 Q1Q1 f REF nQ1 1 24 ADR1 FSEL0 IN 1, 2, nIN 4, 8 2 23 GND GND Q2 50 50 nQ2 3 22 Q0 nQ7 V T 4 21 nQ0 Q7 Q3 8T74S208A Pulldown (2) nQ3 FSEL 1:0 5 20 Q1 nQ6 2 Q4 6 19 nQ1 Q6 nQ4 7 18 GND GND Q5 8 17 V V DDO DDO Pullup SDA nQ5 2 9 10111213 141516 I C Pullup 8 SCL Q6 Pulldown (2) ADR 1:0 nQ6 2 Q7 8T74S208C-01 nQ7 32-Lead VFQFN, 5mm x 5mm x 0.925mm 2016 Integrated Device Technology, Inc. 1 August 22, 2016 Q2 ADR0 nQ2 SCL Q3 SDA nQ3 V DD Q4 nIN nQ4 VT Q5 IN nQ5 FSEL18T74S208C-01 Datasheet Pin Descriptions and Pin Characteristics 1 Table 1. Pin Descriptions Number Name Type Description 2 1 ADR1 Input Pulldown I C Address input. LVCMOS/LVTTL interface levels. 2 GND Power Ground pin. 3Q0 Output Differential output pair 0. LVDS interface levels. 4 nQ0 Output 5Q1 Output Differential output pair 1. LVDS interface levels. 6 nQ1 Output 7 GND Power Ground pin. 8 V Power Output supply pin. DDO 9Q2 Output Differential output pair 2. LVDS interface levels. 10 nQ2 Output 11 Q3 Output Differential output pair 3. LVDS interface levels. 12 nQ3 Output 13 Q4 Output Differential output pair 4. LVDS interface levels. 14 nQ4 Output 15 Q5 Output Differential output pair 5. LVDS interface levels. 16 nQ5 Output 17 V Power Output supply pin. DDO 18 GND Power Ground pin. 19 Q6 Output Differential output pair 6. LVDS interface levels. 20 nQ6 Output 21 Q7 Output Differential output pair 7. LVDS interface levels. 22 nQ7 Output 23 GND Power Ground pin. Frequency divider select control. See Table 3A for function. 24 FSEL0 Input Pulldown LVCMOS/LVTTL interface levels. Frequency divider select control. See Table 3A for function. 25 FSEL1 Input Pulldown LVCMOS/LVTTL interface levels. 26 IN Input Non-inverting differential clock input. RT = 50 termination to V T. Termination Input for termination. Both IN and nIN inputs are internally terminated 50 27 V T Input to this pin. See input termination information in the applications section. 28 nIN Input Inverting differential clock input. RT = 50 termination to V T. 29 V Power Power supply pin. DD 2 I C Data Input/Output. Input. LVCMOS/LVTTL interface levels. 30 SDA I/O Pullup Output: open drain. 2 31 SCL Input Pullup I C Clock Input. LVCMOS/LVTTL interface levels. 2 32 ADR0 Input Pulldown I C Address input. LVCMOS/LVTTL interface levels. NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2016 Integrated Device Technology, Inc. 2 August 22, 2016