DATASHEET ISL6726 FN7654 Rev 0.00 Active Clamp Forward PWM Controller January 31, 2011 The ISL6726 is a highly featured single-ended PWM controller Features intended for applications using the active clamp forward Precision Maximum Duty Cycle and Deadtime Control converter topology in either n- or p-channel active clamp configurations, the asymmetric half-bridge topology, and the 125A Typical Start-up Current standard forward topologies with synchronous rectification. It Adjustable Peak and Average Current Limit Protection is a current-mode PWM controller with many features Programmable Oscillator Frequency designed to simplify its use. Among its many features are a precision oscillator which allows accurate control of the Bi-Directional Synchronization with 180 Phase Shift for deadtime and maximum duty cycle, bi-directional Interleaved Converter Applications synchronization with 180 phase shift for interleaving Adjustable Soft-Start and Selectable Soft-Stop applications, adjustable soft-start and soft-stop, a low power disable mode, and average current limit for brick-wall Selectable Minimum Duty Cycle Clamp for Synchronous overcurrent protection. Rectifier Applications Programmable Slope Compensation This advanced BiCMOS design features low start-up and operating currents, adjustable switching frequency to greater Supports N- and P-Channel Active Clamp FETs than 1MHz, high current FET drivers, and very low propagation Programmable Switch Timing Between Main and Active delays for a fast response to overcurrent faults. Clamp Outputs Programmable Undervoltage Lock-Out (UV) Applications Input Voltage Dependent Duty Cycle Clamp Telecom and Datacom Power Supplies ENABLE Input with Low Power Disable AC/DC Power Supplies Internal Over-Temperature Protection Battery Chargers Pb-Free (RoHS Compliant) +VIN OUTM +VIN LEVEL SHIFT LEVEL SHIFT OUTAC OUTAC OUTM OUTAC -VIN -VIN N- or P- CHANNEL ACTIVE CLAMP FORWARD ASYMMETRIC HALF-BRIDGE FN7654 Rev 0.00 Page 1 of 21 January 31, 2011ISL6726 Pin Configuration ISL6726 (20 LD QSOP) TOP VIEW SYNC 1 20 SS DCLIM 2 MODE 19 UV 3 18 DELAY ENABLE 4 17 VREF RTC 5 16 GND CT 6 15 OUTM ISET 7 14 VDD VERR 8 13 OUTAC FB 9 12 SLOPE CS 10 11 IOUT Pin Descriptions PIN SYMBOL DESCRIPTION 1 SYNC A bi-directional edge-sensitive signal used to synchronize multiple devices together. If the SYNC pins of two units are connected, they will synchronize 180 degrees out of phase with each other. This feature facilitates the design of interleaved topologies. If more than two units are connected, one will be the master unit and the rest will be slave units. All of the slave units will synchronize 180 degrees out-of-phase with the master. The master designation is not fixed or predetermined and is self-arbitrating. The master is determined by the fastest running oscillator on a dynamic basis. SYNC may also be used to synchronize to an external clock. 2 DCLIM Used in conjunction with UV, DCLIM creates a duty cycle clamp that is dependent on the input voltage. As the input voltage increases, the maximum allowed duty cycle decreases. This feature is necessary in the active clamp forward to help prevent transformer core saturation during transients. A resistor divider from VREF sets the threshold of DCLIM. 3 UV Sets the user programmable undervoltage threshold. Placing a resistor divider from the input voltage to ground and set to 1.00V determines the minimum operating voltage. The amount of hysteresis is determined by an internal current source and set by the external impedance of the divider. The current source is active when UV is below 1V. 4 ENABLE A logic level signal used to enable the IC. When the input is open, the IC is enabled and a soft-start cycle begins if no fault conditions are present. When pulled low, the outputs are disabled and the IC enters a low power sleep state. If soft-stop is enabled, a logic 0 on ENABLE forces a soft-stop prior to entering the low power sleep state. 5 RTC The oscillator timing capacitor charge/discharge current control pin. A resistor is connected between this pin and GND and determines the magnitude of the charge and discharge current. The charge current is nominally 2x the current flowing into the resistor. The discharge current is nominally 8x the current flowing into the resistor. The ratio of the charge to discharge current is fixed and sets the maximum duty cycle at 80%. 6 CT The oscillator timing capacitor is connected between this pin and GND. 7 ISET Controls the peak and average current limit thresholds. A voltage up to 1.0V may be applied to ISET. 8 VERR The error voltage input to the PWM comparator and the compensation connection for the average current loop control. VERR requires an external pull-up resistor to VREF. A typical application connects the photo-transistor output of an opto-coupler between VERR and GND. 9 FB FB is the inverting input to the average current error amplifier (IEA). The amplifier is used as the error amplifier for the average current limit control loop. If the amplifier is not used, FB should be grounded. The amplifier is normally configured as an integrator. 10 CS The current sense input to the IC. Provides information to the PWM, the peak overcurrent protection comparators, and the average current limit circuitry. The CS pin is shorted to GND when the PWM output pulse terminates. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal logic and the turn off of the external power switch. 11 IOUT Output of the sample and hold buffer amplifier that captures and averages the CS signal. With a nominal 4x multiplier and the ability to scale the signal externally with a resistor divider, the average current limit can be set independently of the peak current limit. FN7654 Rev 0.00 Page 2 of 21 January 31, 2011