2.5 V/3.3 V 1:5 Differential MC100ES6014 ECL/PECL/HSTL/LVDS Clock Driver Product Discontinuance Notice Last Time Buy Expires on (12/3/2013) DATA SHEET The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the V MC100ES6014 BB output is used). HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 even if only one DT SUFFIX output is being used. If an output pair is unused, both outputs may be left open 20-LEAD TSSOP PACKAGE CASE 948E-03 (unterminated) without affecting skew. ) is synchronous, outputs are enabled/disabled in the The common enable (EN LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock therefore, all associated specification limits are referenced to the negative edge of the clock input. EJ SUFFIX The MC100ES6014, as with most other ECL devices, can be operated from a 20-LEAD TSSOP PACKAGE positive V supply in PECL mode. This allows the ES6014 to be used for high Pb-FREE PACKAGE CC CASE 948E-03 performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK input pin operation is limited to a V 3.0 V in PECL mode, or V 3.0 V in CC EE ECL mode. Designers can take advantage of the ES6014 s performance to ORDERING INFORMATION distribute low skew clocks across the backplane or the board. Device Package Features MC100ES6014EJ TSSOP-20 (Pb-Free) 25 ps Within Device Skew MC100ES6014EJR2 TSSOP-20 (Pb-Free) 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: V = 2.375 V to 3.8 V with V = 0 V CC EE = 0 V with V = 2.375 V to 3.8 V ECL Mode: V CC EE LVDS and HSTL Input Compatible Open Input Default State 20-Lead Pb-Free Package Available Replacement part: ICS853S014I MC100ES6014 REVISION 4 DECEMBER 18, 2012 1 2012 Integrated Device Technology, Inc.MC100ES6014 Data Sheet 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver V EN V CLK1 CLK1 V CLK0 CLK0 CLK SEL V CC CC BB EE 20 19 18 17 16 15 14 13 12 11 10 D Q 1 2 3 4 5678 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Warning: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Figure 1. 20-Lead Pinout (Top View) and Logic Diagram Table 1. Pin Description Table 2. Function Table Pin Function CLK0 CLK1 CLK SEL EN Q CLK0*, CLK0** ECL/PECL/HSTL CLK Input L X L L L H X L L H CLK1*, CLK1** ECL/PECL/HSTL CLK Input X L H L L Q0:4, Q0:4 ECL/PECL Outputs X H H L H X X X H L* CLK SEL* ECL/PECL Active Clock Select Input * On next negative transition of CLK0 or CLK1 EN* ECL Sync Enable V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE * Pins will default LOW when left open. ** Pins will default to V /2 when left open. CC Table 3. General specifications Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 2000 V Machine Model > 200 V Charged Device Model > 1500 V Thermal Resistance (Junction-to-Ambient) 0 LFPM, 20 TSSOP 140 C/W 500 LFPM, 20 TSSOP 100 C/W Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test MC100ES6014 REVISION 4 DECEMBER 18, 2012 2 2012 Integrated Device Technology, Inc.