74LVX16373 LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS HIGH SPEED : t = 5.4 ns (MAX.) at V =3V PD CC 5V TOLERANT INPUTS POWER DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: V =0.8V, V =2V atV =3V IL IH CC TSSOP LOW POWER DISSIPATION: I =4 A (MAX.) at T =25C CC A LOW NOISE: V =0.3V (TYP.)atV =3.3V ORDER CODES OLP CC SYMMETRICAL OUTPUT IMPEDANCE: PACKAGE TUBE T & R I = I =4mA(MIN)atV =3V OH OL CC TSSOP 74LVX16373TTR BALANCED PROPAGATION DELAYS: t t PLH PHL PIN CONNECTION OPERATING VOLTAGE RANGE: V (OPR) = 2V to 3.6V (1.2V Data Retention) CC PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon 2 gate and double-layer metal wiring C MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high imped- ance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 1/10 Obsolete Product(s) - Obsolete Product(s)74LVX16373 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION IEC LOGIC SYMBOLS PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUT OE LE D Q HX X Z L L X NO CHANGE * LH L L LH H H X : Dont Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level. 2/10 Obsolete Product(s) - Obsolete Product(s)