M74HC126TTR STMicroelectronics

M74HC126 Quad bus buffer (3-state) Datasheet - production data Balanced propagation delays: t t PLH PHL Wide operating voltage range: V (opr) = 2 V to 6 V CC Pin and function compatible with 74 series 126 ESD performance SO14 TSSOP14 CDM: 1 kV HBM: 2 kV MM: 200 V Features Description High-speed: t = 8 ns (typ.) at V = 6 V The M74HC126 is a high-speed CMOS quad PD CC buffer (3-state) fabricated with silicon gate Low power dissipation: 2 C MOS technology. I = 4 A (max.) at T = 25 C CC A The device requires the 3-state control input, G, to High noise immunity: be set high to place the output into high V = V = 28 % V (min) NIH NIL CC impedance state. Symmetrical output impedance: I = I = 6 mA (min.) All inputs are equipped with protection circuits OH OL against static discharge and transient excess voltage. Table 1. Device summary Order code Temp. range Package Packaging Marking M74HC126RM13TR -55 C to 125 C S014 74HC126 (1) M74HC126YRM13TR -40 C to 125 C SO14 (automotive grade) 74HC126Y Tape and reel M74HC126TTR -55 C to 125 C TSSOP14 HC126 (1) M74HC126YTTR -40 C to 125 C TSSOP14 (automotive grade) HC126Y 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent. December 2013 DocID8021 Rev 3 1/14 This is information on a product in full production. www.st.comContents M74HC126 Contents 1 Pin information . 3 2 Functional description . 4 3 Electrical characteristics . 5 4 Package information 10 4.1 SO14 package information .11 4.2 TSSOP14 package information 12 5 Ordering information . 13 6 Revision history . 13 2/14 DocID8021 Rev 3