7 TSM70N1R4 Taiwan Semiconductor N-Channel Power MOSFET 700V, 3.3A, 1.4 FEATURES KEY PERFORMANCE PARAMETERS Super-Junction technology PARAMETER VALUE UNIT High performance due to small figure-of-merit V 700 V DS High ruggedness performance R (max) 1.4 DS(on) High commutation performance Q 7.7 nC g APPLICATION Power Supply Lighting TO-251 (IPAK) TO-252 (DPAK) Notes: MSL 3 (Moisture Sensitivity Level) for TO-252 (D-PAK) per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) C PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 700 V DS Gate-Source Voltage V 30 V GS T = 25C 3.3 C (Note 1) Continuous Drain Current I A D T = 100C 2.0 C (Note 2) Pulsed Drain Current I 9.9 A DM Total Power Dissipation T = 25C P 38 W C DTOT (Note 3) Single Pulsed Avalanche Energy E 64 mJ AS (Note 3) Single Pulsed Avalanche Current I 1.6 A AS Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT UNIT Junction to Case Thermal Resistance R 3.3 C/W JC Junction to Ambient Thermal Resistance R 62 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JA CA design. R shown below for single device operation on FR-4 PCB in still air. JA Document Number: DS P0000136 1 Version: D1706 7 TSM70N1R4 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) C PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 4) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 700 -- -- V GS D DSS Gate Threshold Voltage V = V , I = 250A V 2 3 4 DS GS D GS(TH) V Gate Body Leakage V = 30V, V = 0V I -- -- 100 nA GS DS GSS Zero Gate Voltage Drain Current V = 700V, V = 0V I -- -- 1 DS GS DSS A V = 10V, I = 1.2A -- 0.9 1.4 Drain-Source On-State Resistance R GS D DS(ON) (Note 5) Dynamic Total Gate Charge Q -- 7.7 -- g V = 380V, I = 3.3A, DS D Gate-Source Charge Q -- 1.9 -- gs nC V = 10V GS Gate-Drain Charge Q -- 2.8 -- gd Input Capacitance C -- 370 -- V = 100V, V = 0V, iss DS GS pF Output Capacitance f = 1.0MHz C -- 34 -- oss Gate Resistance F = 1MHz, open drain R -- 3.4 -- g (Note 6) Switching Turn-On Delay Time t -- 14 -- d(on) V = 380V, DD Turn-On Rise Time t -- 22 -- r R = 25, ns GEN Turn-Off Delay Time t -- 24 -- d(off) I = 3.3A, V = 10V, D GS Turn-Off Fall Time t -- 20 -- f (Note 4) Source-Drain Diode Forward On Voltage -- -- 1.4 V I = 3.3A, V = 0V V S GS SD Reverse Recovery Time -- 163 -- ns t V = 200V, I = 2A rr R S Reverse Recovery Charge dI /dt = 100A/s Q -- 1 -- C F rr Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature o 3. L = 50mH, I = 1.6A, V = 50V, R = 25, Starting T = 25 C AS DD G J 4. Pulse test: PW 300s, duty cycle 2% 5. For DESIGN AID ONLY, not subject to production testing. 6. Switching time is essentially independent of operating temperature. Document Number: DS P0000136 2 Version: D1706