TC74LVXC3245FS(S,F) Toshiba

TC74LVXC3245FS TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVXC3245FS Dual Supply Octal Configurable Voltage Interface Bus Transceiver The TC74LVXC3245FS is a dual supply, advanced high-speed CMOS octal configurable voltage interface bus transceiver fabricated with silicon gate CMOS technology. Designed for use as an interface between a 3.3 V bus and a 3.3V to 5 V bus in mixed 3.3 V/5 V supply systems it achieves high-speed operation while maintaining the CMOS low power dissipation. It is intended for 2 way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input. The enable input ( G ) can be used to disable the device Weight: 0.14 g (typ.) so that the buses are effectively isolated. The A-port interfaces with the 3.3-V bus, the B-port with the 3.3V to 5V bus. This device will allow the V voltage source pin and I/O pins on the CCB B port to float when G is H. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features Bi-directional interface between 3 V and 5 V buses High-speed: t = 8.5 ns (max) pd (V = 3.3 V, V = 5.0 V) CCA CCB Low power dissipation: I = 8 A (max) (Ta = 25C) CC Symmetrical output impedance: I = 24 mA (min) OUTA I = 24 mA (min) OUTB (V = V = 3.0 V) CCA CCB Low noise: V = 1.5 V (max) OLP Flexible V operating range CCB Allows B port and V to float simultaneously when G is H CCB Package: SSOP (shrink small outline package) Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result. All floating (high impedance) bus pin must have their input levels fixed by means of pull-up or pull-down resistors. 1 2012-09-10 TC74LVXC3245FS Pin Assignment (top view) IEC Logic Symbol (22) G G3 V 1 24 V CCA CCB (2) DIR 3 EN 1 (BA) DIR 2 23 NC 3 EN 2 (AB) A1 22 G (3) (21) 3 A1 1 B1 A2 4 21 B1 2 (20) (4) A2 B2 A3 5 20 B2 (19) (5) A4 6 19 B3 A3 B3 (18) A5 7 18 B4 (6) A4 B4 A6 8 17 B5 (17) (7) A5 B5 A7 9 16 B6 (16) (8) A6 B6 A8 10 15 B7 (15) (9) A7 B7 GND 11 14 B8 (10) (14) GND 12 13 GND A8 B8 Truth Table Inputs Function Outputs G DIR A-Bus B-Bus L L A = B Output Input L H B = A Input Output H X Z High impedance X: Dont care Z: High impedance 2 2012-09-10