6.15 mm Si7540ADP www.vishay.com Vishay Siliconix N- and P-Channel 20 V (D-S) MOSFET FEATURES PowerPAK SO-8 Dual D TrenchFET power MOSFETs 1 D 1 8 D Thermally enhanced PowerPAK 2 7 D 6 2 100 % R tested g 5 Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 1 2 S 1 3 G APPLICATIONS 1 1 44 S 2 D S 1 2 G DC/DC converters 2 Top View Bottom View Synchronous buck converter PRODUCT SUMMARY Synchronous rectifier G 2 N-CHANNEL P-CHANNEL Load switch G 1 V (V) 20 -20 DS Motor drive switch R ( ) at V = 4.5 V 0.0150 0.0280 DS(on) GS R ( ) at V = 2.5 V 0.0195 0.0430 DS(on) GS S 1 D Q typ. (nC) 8.5 16 2 g N-Channel MOSFET a, b I (A) 12 9 D P-Channel MOSFET Configuration N- and p-pair ORDERING INFORMATION Package PowerPAK SO-8 Lead (Pb)-free and halogen-free Si7540ADP-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A N-CHANNEL P-CHANNEL PARAMETER SYMBOL UNIT 10 s STEADY 10 s STEADY Drain-source voltage V 20 -20 DS V Gate-source voltage V 12 GS T = 25 C 12 8 -9 -6.1 A a, b Continuous drain current (T = 150 C) I J D T = 70 C 9.8 6.5 -7.3 -4.9 A A Pulsed drain current I 35 -25 DM b Continuous source current (diode conduction) I 2.9 1.3 -2.9 -1.3 S T = 25 C 3.5 1.6 3.5 1.6 A b Maximum power dissipation P W D T = 70 C 2.3 1 2.3 1 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS N-CHANNEL P-CHANNEL PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 25 35 25 35 thJA C/W Maximum junction-to-case (drain) Steady state R 4.6 6 4.8 6.3 thJC Notes a. Based on silicon capability only. b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: Manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 80 C/W. S16-2274-Rev. C, 14-Nov-16 Document Number: 62951 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5.15 mmSi7540ADP www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAXUNIT Static V = 0 V, I = 250 A N-Ch 20 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = -250 A P-Ch -20 - - GS D I = 250 A N-Ch - 17 - D V temperature coefficient V /T DS DS J I = -250 A P-Ch - -11 - D mV/C I = 250 A N-Ch - -3.7 - D V temperature coefficient V /T GS(th) GS(th) J I = -250 A P-Ch - 5.5 - D V = V , I = 250 A N-Ch 0.6 - 1.4 DS GS D Gate threshold voltage V V GS(th) V = V , I = -250 A P-Ch -0.6 - -1.4 DS GS D N-Ch - - 100 Gate-body leakage I V = 0 V, V = 12 V nA GSS DS GS P-Ch - - 100 V = 20 V, V = 0 V N-Ch - - 1 DS GS V = -20 V, V = 0 V P-Ch - - -1 DS GS Zero gate voltage drain current I A DSS V = 20 V, V = 0 V, T = 55 C N-Ch - - 10 DS GS J V = -20 V, V = 0 V, T = 55 C P-Ch - - -10 DS GS J V 5 V, V = 4.5 V N-Ch 20 - - DS GS b On-state drain current I A D(on) V -5 V, V = -4.5 V P-Ch -20 - - DS GS V = 4.5 V, I = 12 A N-Ch - 0.0115 0.0150 GS D V = -4.5 V, I = -9 A P-Ch - 0.0220 0.0280 GS D b Drain-source on-state resistance R DS(on) V = 2.5 V, I = 9 A N-Ch - 0.0150 0.0195 GS D V = -2.5 V, I = -6 A P-Ch - 0.0330 0.0430 GS D V = 10 V, I = 12 A N-Ch - 55 - DS D b Forward transconductance g S fs V = -10 V, I = -9 A P-Ch - 24 - DS D a Dynamic N-Ch - 915 - Input capacitance C iss P-Ch - 1310 - N-channel V = 10 V, V = 0 V, f = 1 MHz DS GS N-Ch - 235 - Output capacitance C pF oss P-Ch - 310 - P-channel V = -10 V, V = 0 V, f = 1 MHz DS GS N-Ch - 110 - Reverse transfer capacitance C rss P-Ch - 270 - V = 10 V, V = 10 V, I = 12 A N-Ch - 18 27 DS GS D V = -10 V, V = -10 V, I = -9 A P-Ch - 32 48 DS GS D Total gate charge Q g N-Ch - 8.5 13 P-Ch - 16 24 N-channel nC V = 10 V, V = 4.5 V, I = 12 A DS GS D N-Ch - 1.8 - Gate-source charge Q gs P-Ch - 2.3 - P-channel V = -10 V, V = -4.5 V, I = -9 A DS GS D N-Ch - 2.2 - Gate-drain charge Q gd P-Ch - 6 - N-Ch 0.6 3.2 6.4 Gate resistance R f = 1 MHz g P-Ch 0.2 1 2 S16-2274-Rev. C, 14-Nov-16 Document Number: 62951 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000