P GND V IN GH GL C GND VDRV SiC620, SiC620A www.vishay.com Vishay Siliconix 60 A VRPower Integrated Power Stage DESCRIPTION FEATURES Thermally enhanced PowerPAK MLP55-31L The SiC620 and SiC620A are integrated power stage package solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density Vishays Gen IV MOSFET technology and a performance. Packaged in Vishays proprietary 5 mm x 5 mm low-side MOSFET with integrated Schottky MLP package, SiC620 and SiC620A enables voltage diode regulator designs to deliver up to 60 A continuous current Delivers up to 60 A continuous current per phase. 95 % peak efficiency The internal power MOSFETs utilizes Vishays High frequency operation up to 1.5 MHz state-of-the-art Gen IV TrenchFET technology that delivers Power MOSFETs optimized for 12 V input stage industry benchmark performance to significantly reduce 3.3 V (SiC620A) / 5 V (SiC620) PWM logic with tri-state and switching and conduction losses. hold-off The SiC620 and SiC620A incorporates an advanced Zero current detect control for light load efficiency MOSFET gate driver IC that features high current driving improvement capability, adaptive dead-time control, an integrated Low PWM propagation delay (< 20 ns) bootstrap Schottky diode, a thermal warning (THWn) that alerts the system of excessive junction temperature, and Thermal monitor flag zero current detect to improve light load efficiency. The Under voltage lockout for V CIN drivers are also compatible with a wide range of PWM Material categorization: for definitions of compliance controllers and supports tri-state PWM, 3.3 V (SiC620A) / please see www.vishay.com/doc 99912 5 V (SiC620) PWM logic. APPLICATIONS Multi-phase VRDs for CPU, GPU, and memory TYPICAL APPLICATION DIAGRAM 5V V IN BOOT PHASE V CIN ZCD EN V SWH DSBL V OUT Gate PWM driver PWM controller THWn Fig. 1 - SiC620 and SiC620A Typical Application Diagram S14-2385-Rev. E, 08-Dec-14 Document Number: 62922 1 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000P V GND SWH P V GND SWH P V GND SWH GL P GND P GND V V DRV IN THWn V IN DSBL V IN SiC620, SiC620A www.vishay.com Vishay Siliconix PINOUT CONFIGURATION 33 31 30 29 28 27 26 25 24 GL 24 25 26 27 28 29 30 31 PWM PWM 1 1 23 V V 23 SWH SWH GL GL ZCD EN 2 2 ZCD EN 22 V V 22 SWH SWH 32 CGND V 3 CGND 3 V CIN 21 V V 21 CIN SWH SWH C C 4 4 GND 20 V V 20 GND SWH SWH 35 BOOT BOOT 5 5 PGND 19 V V 19 SWH SWH PGND GH 6 6 HG 18 V V 18 SWH SWH 34 VIN 7 V 17 7 PHASE 17 V PHASE SWH SWH VIN V 8 16 V V 16 8 V IN SWH SWH IN 9 10 11 12 13 14 15 15 14 13 12 11 10 9 Top view Bottom view Fig. 2 - SiC620 and SiC620A Pin Configuration PIN CONFIGURATION PIN NUMBER NAME FUNCTION 1PWM PWM control input 2 ZCD EN ZCD control. Active low 3V Supply voltage for internal logic circuitry CIN 4, 32 C Analog ground for the driver IC GND 5 BOOT High-side driver bootstrap voltage 6 GH High-side gate signal 7 PHASE Return path of high-side gate driver 8 to 11, 34 V Power stage input voltage. Drain of high-side MOSFET IN 12 to 15, 28, 35 P Power ground GND 16 to 26 V Switch node of the power stage SWH 27, 33 GL Low-side gate signal 29 V Supply voltage for internal gate driver DRV 30 THWn Thermal warning open drain output 31 DSBL Disable pin. Active low ORDERING INFORMATION PART NUMBER PACKAGE MARKING CODE OPTION SiC620CD-T1-GE3 PowerPAK MLP55-31L SiC620 5 V PWM optimized SiC620ACD-T1-GE3 PowerPAK MLP55-31L SiC620A 3.3 V PWM optimized SiC620DB / SiC620ADB Reference board S14-2385-Rev. E, 08-Dec-14 Document Number: 62922 2 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 P V GND SWH P V GND SWH P GND V SWH P GL GND P GND V V IN DRV V THWn IN V DSBL IN