EF-DI-LAUI-SITE Xilinx

40G/50G High Speed Ethernet Subsystem v2.4 LogiCORE IP Product Guide Vivado Design Suite PG211 December 5, 2018Table of Contents IP Facts Chapter 1: Overview Feature Summary 5 Applications 6 Licensing and Ordering . 7 Chapter 2: Product Specification Typical Operation . 10 Statistics Gathering . 10 Testability Functions 10 Pause Operation 11 Standards . 11 Performance and Resource Utilization 11 Latency . 11 Port Descriptions . 12 Auto-Negotiation (AN) and Link Training (LT) 46 PCS Variant 62 AXI4-Lite Register Space . 72 Chapter 3: Designing with the Core General Design Guidelines 131 Clocking 132 LogiCORE Example Design Clocking and Resets 138 Serdes Data Mapping for GTM . 142 IEEE PTP 1588v2 for 40G/50G Subsystem 145 RS-FEC Support 158 Status/Control Interface 162 Chapter 4: Design Flow Steps Customizing and Designing the Core 167 Constraining the Core 174 Simulation . 175 Synthesis and Implementation . 176 40G/50G High Speed Ethernet v2.4 2 Send Feedback PG211 December 5, 2018 www.xilinx.com