ADVANCED LINEAR DEVICES, INC. ALD1105 DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR GENERAL DESCRIPTION APPLICATIONS The ALD1105 is a monolithic dual N-channel and dual P-channel comple- Precision current mirrors mentary matched transistor pair intended for a broad range of analog Complementary push-pull linear drives applications. These enhancement-mode transistors are manufactured Analog switches with Advanced Linear Devices enhanced ACMOS silicon gate CMOS Choppers process. It consists of an ALD1116 N-channel MOSFET pair and an Differential amplifier input stage ALD1117 P-channel MOSFET pair in one package. The ALD1105 is a low Voltage comparator drain current, low leakage current version of the ALD1103. Data converters Sample and Hold The ALD1105 offers high input impedance and negative current tempera- Analog inverter ture coefficient. The transistor pair is matched for minimum offset voltage Precision matched current sources and differential thermal response, and it is designed for precision signal switching and amplifying applications in +2V to +10V systems where low PIN CONFIGURATION input bias current, low input capacitance and fast switching speed are desired. Since these are MOSFET devices, they feature very large DN1 1 14 DN2 (almost infinite) current gain in a low frequency, or near DC, operating environment. When used in pairs, a dual CMOS analog switch can be GN1 2 13 GN2 constructed. In addition, the ALD1105 is intended as a building block for differential amplifier input stages, transmission gates, and multiplexer SN1 3 12 SN2 applications. - V 4 + 11 V The ALD1105 is suitable for use in precision applications which require very high current gain, beta, such as current mirrors and current sources. 5 DP1 10 DP2 The high input impedance and the high DC current gain of the Field Effect Transistors result in extremely low current loss through the control gate. GP2 GP1 6 9 The DC current gain is limited by the gate input leakage current, which is specified at 100pA at room temperature. For example, DC beta of the SP1 7 8 SP2 device at a drain current of 3mA at 25C is = 3mA/100pA = 300,000,000. TOP VIEW SBL, PBL PACKAGES FEATURES Thermal tracking between N-channel and P-channel pairs Low threshold voltage of 0.7V for both N-channel & BLOCK DIAGRAM P-channel MOSFETS N GATE 1 (2) Low input capacitance Low Vos -- 10mV 13 High input impedance -- 10 typical N SOURCE 1 (3) N DRAIN 1 (1) Low input and output leakage currents Negative current (I ) temperature coefficient DS SUBSTRATE (4) Enhancement mode (normally off) 9 N DRAIN 2 (14) N SOURCE 2 (12) DC current gain 10 Matched N-channel and matched P-channel in one package RoHS compliant N GATE 2 (13) ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) P GATE 1 (6) Operating Temperature Range* 0C to +70C0C to +70C P DRAIN 1 (5) P SOURCE 1 (7) 14-Pin 14-Pin SUBSTRATE (11) SOIC Plastic Dip Package Package P DRAIN 2 (10) P SOURCE 2 (8) ALD1105SBL ALD1105PBL * Contact factory for high temperature versions. P GATE 2 (9) 2021 Advanced Linear Devices, Inc., Vers. 2.2 www.aldinc.com 1 of 8ABSOLUTE MAXIMUM RATINGS Drain-source voltage, V 10V DS Gate-source voltage, V 10V GS Power dissipation 500mW Operating temperature range SBL, PBL packages 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS T = 25C unless otherwise specified A N - Channel Test P - Channel Test Parameter Symbol Min Typ Max Unit Conditions Min Typ Max Unit Conditions Gate Threshold V 0.4 0.7 1.0 V I = 1A V = V -0.4 -0.7 -1.2 V I = -1A V = V T DS GS DS DS GS DS Voltage Offset Voltage V 210 mV I = 10A V = V 210 mV I = -10A V = V OS DS GS DS DS GS DS V - V GS1 GS2 Gate Threshold Temperature TC -1.2 mV/C -1.3 mV/C VT Drift On Drain I 3 4.8 mA V = V = 5V -1.3 -2 mA V = V = -5V DS(ON) GS DS GS DS Current Trans-. G 1 1.8 mmho V = 5V I = 10mA 0.25 0.67 mmho V = -5V I = -10mA fs DS DS DS DS conductance Mismatch G 0.5 % 0.5 % fs Output G 200 mho V = 5V I = 10mA 40 mho V = -5V I = -10mA OS DS DS DS DS Conductance Drain Source R 350 500 V = 0.1V V = 5V 1200 1800 V = -0.1V V = -5V DS(ON) DS GS DS GS ON Resistance Drain Source ON Resistance R 0.5 % V = 0.1V V = 5V 0.5 % V = -0.1V V = -5V DS(ON) DS GS DS GS Mismatch Drain Source Breakdown BV 10 V I = 1A V = 0V -10 V I = -1A V = 0V DSS DS GS DS GS Voltage Off Drain I 10 400 pA V = 10V I = 0V 10 400 pA V = -10V V = 0V DS(OFF) DS GS DS GS Current 4 nA T = 125C4nAT = 125C A A Gate Leakage I 1 100 pA V = 0V V = 10V 1 100 pA V = 0V V = -10V GSS DS GS DS GS Current 10 nA T = 125C10nAT = 125C A A Input C 1 3 pF 1 3 pF ISS Capacitance ALD1105 Advanced Linear Devices 2 of 8