e TM ADVANCED EPAD LINEAR DEVICES, INC. ALD110800A/ALD110800/ALD110900A/ALD110900 QUAD/DUAL N-CHANNEL ZERO THRESHOLD EPAD V = +0.00V GS(th) PRECISION MATCHED PAIR MOSFET ARRAY GENERAL DESCRIPTION FEATURES ALD110800A/ALD110800/ALD110900A/ALD110900 are high precision Precision zero threshold voltage mode monolithic quad/dual N-Channel MOSFETs matched at the factory using Nominal R V = 0.00V of 104K DS(ON) GS ALDs proven EPAD CMOS technology. These devices are members of Matched MOSFET-to-MOSFET characteristics the EPAD Matched Pair MOSFET Family. Tight lot-to-lot parametric control V match (V ) to 2mV and 10mV max. GS(th) OS Intended for low voltage small signal applications, the ALD110800/ Positive, zero, and negative V tempco GS(th) ALD110900 features Zero-Threshold voltage, which reduces or elimi- Low input capacitance nates input to output voltage level shift, including circuits where the signal Low input/output leakage currents is referenced to GND or V+. This feature greatly reduces output signal voltage level shift and enhances signal operating range, especially for APPLICATIONS very low operating voltage environments. With these zero threshold de- Energy harvesting circuits vices, an analog circuit with multiple stages can be constructed to oper- Very low voltage analog and digital circuits ate at extremely low supply or bias voltage levels. For example, an input Zero power fail safe circuits amplifier stage operating at 0.2V supply voltage has been demonstrated. Backup battery circuits & power failure detector ALD110800A/ALD110800/ALD110900A/ALD110900 matched pair Low level voltage clamp & zero crossing detector MOSFETs are designed for exceptional device electrical characteristics Source followers and buffers matching with the threshold voltage set precisely at +0.00V +/-0.01V, fea- Precision current mirrors and current sources turing a typical offset voltage of only +/-0.001V (1mV). As these devices Capacitives probes and sensor interfaces are on the same monolithic chip, they also exhibit excellent tempco track- Charge detectors and charge integrators ing characteristics. They are versatile as design components for a broad Differential amplifier input stage range of analog applications such as basic building blocks for current High side switches sources, differential amplifier input stages, transmission gates, and multi- Peak detectors and level shifters plexer applications. Sample and Hold Current multipliers Besides matched pair electrical characteristics, each individual MOSFET Analog switches / multiplexers also exhibits well controlled parameters, enabling the user to depend on Voltage comparators and level shifters tight design limits. Even units from different batches and different date of manufacture have correspondingly well matched characteristics. PIN CONFIGURATIONS ALD110800 These devices are built for minimum offset voltage and differential ther- mal response, and they are designed for switching and amplifying appli- - - V V cations in +0.2V to +10V systems where low input bias current, low input IC* 1 16 IC* capacitance, and fast switching speed are desired. The V of these GS(th) 15 G G 2 N2 devices is set at +0.00V, which classifies them as both enhancement mode N1 M 2 M 1 and depletion mode devices. When the gate is set at 0.00V, the drain 14 D 3 D N1 N2 current is +1A V = 0.1V, which allows a class of circuits with output DS + + S 4 13 voltage level biased at or near input voltage level without voltage level 12 V V shift. These devices exhibit well controlled turn-off and sub-threshold - - 5 V 12 S V 34 characteristics of standard enhancement mode MOSFETs. D 6 11 D N4 N3 M 4 M 3 The ALD110800A/ALD110800/ALD110900A/ALD110900 feature high in- 12 8 G 7 10 G put impedance (10 ) and high DC current gain (>10 ). A sample calcu- N4 N3 lation of the DC current gain at a drain current of 3mA and input leakage 8 9 IC* IC* - - current of 30pA at 25C is 3mA/30pA = 100,000,000. For most applica- V V tions, connect the V+ pin to the most positive voltage and the V- and IC SCL, PCL PACKAGES pins to the most negative voltage in the system. All other pins must have voltages within these voltage limits at all times. ALD110900 - - V V ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) 1 8 IC* IC* Operating Temperature Range* G 2 7 G N2 0C to +70C0C to +70C N1 M 1 M 2 D 3 6 D N1 N2 16-Pin 16-Pin 8-Pin 8-Pin SOIC Plastic Dip SOIC Plastic Dip - - S 4 V 12 V 5 Package Package Package Package ALD110800ASCL ALD110800APCL ALD110900ASAL ALD110900APAL SAL, PAL PACKAGES ALD110800SCL ALD110800PCL ALD110900SAL ALD110900PAL *IC pins are internally connected, connect to V- * Contact factory for industrial temp. range or user-specified threshold voltage values. 2019 Advanced Linear Devices, Inc., Vers. 2.5 www.aldinc.com 1 of 12 E N A D E L BABSOLUTE MAXIMUM RATINGS Drain-Source voltage, V 10.6V DS Gate-Source voltage, V 10.6V GS Power dissipation 500 mW Operating temperature range SCL, PCL, SAL, PAL 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS + - V = +5V V = GND T = 25C unless otherwise specified A ALD110800A/ALD110900A ALD110800/ALD110900 Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions Gate Threshold Voltage V -0.02 0.00 0.02 -0.02 0.00 0.02 V I =1A, V = 0.1V GS(th) DS DS Offset Voltage V 1.8 3.8 2 10 mV OS V -V GS(th)1 GS(th)2 Offset Voltage Tempco TC 55 V/CV = V VOS DS1 DS2 Gate Threshold Voltage TC -1.7 -1.7 mV/CI = 1A, V = 0.1V VGS(th) DS DS Tempco 0.0 0.0 I = 20A, V = 0.1V DS DS +1.6 +1.6 I = 40A, V = 0.1V DS DS Drain Source On Current I 12.0 12.0 mA V = +9.5V, V = +5V DS(ON) GS DS 3.0 3.0 V = +4.0V, V = +5V GS DS Forward Transconductance G 1.4 1.4 mmho V = +4.0V FS GS V = +9.0V DS Transconductance Mismatch G 1.8 1.8 % FS Output Conductance G 68 68 mho V = +4.0V OS GS V = +9.0V DS Drain Source On Resistance R 500 500 V = +4.0V DS(ON) GS V = +0.1V DS Drain Source On Resistance R 104 104 K V = +0.0V DS(ON) GS V = +0.1V DS Drain Source On Resistance R 55 %V = +4.0V DS(ON) GS Tolerance V = +0.1V DS Drain Source On Resistance R 0.5 0.5 % DS(ON) Mismatch - Drain Source Breakdown BV 10 10 V V = V = -1.0V DSX GS Voltage I = 1.0A DS 1 Drain Source Leakage Current I 10 400 10 400 pA V = -1.0V, V =+5V DS(OFF) GS DS - V = -5V 44nAT = 125C A 1 Gate Leakage Current I 5 200 5 200 pA V = +5V, V = 0V GSS GS DS 11nAT =125C A Input Capacitance C 2.5 2.5 pF ISS Transfer Reverse Capacitance C 0.1 0.1 pF RSS + Turn-on Delay Time t 10 10 ns V = 5V, R = 5K on L + Turn-off Delay Time t 10 10 ns V = 5V, R = 5K off L Crosstalk 60 60 dB f = 100KHz 1 Notes: Consists of junction leakage currents ALD110800A/ALD110800/ Advanced Linear Devices 2 of 12 ALD110900A/ALD110900, Vers. 2.5