e TM ADVANCED EPAD LINEAR DEVICES, INC. ALD110808A/ALD110808/ALD110908A/ALD110908 QUAD/DUAL N-CHANNEL ENHANCEMENT MODE EPAD V = +0.80V GS(th) PRECISION MATCHED PAIR MOSFET ARRAY GENERAL DESCRIPTION APPLICATIONS ALD110808A/ALD110808/ALD110908A/ALD110908 are high precision Precision current mirrors monolithic quad/dual enhancement mode N-Channel MOSFETs matched Precision current sources at the factory using ALDs proven EPAD CMOS technology. These de- Voltage choppers vices are intended for low voltage, small signal applications. Differential amplifier input stage Voltage comparator These MOSFET devices are built on the same monolithic chip, so they Voltage bias circuits exhibit excellent temperature tracking characteristics. They are versatile Sample and Hold as circuit elements and are useful design component for a broad range of Analog inverter analog applications. They are basic building blocks for current sources, Level shifters differential amplifier input stages, transmission gates, and multiplexer Source followers and buffers applications. For most applications, connect the V+ pin to the most posi- Current multipliers tive voltage and the V- and IC pins to the most negative voltage in the Analog switches / multiplexers system. All other pins must have voltages within these voltage limits at all times. ALD110808/ALD110908 devices are built for minimum offset voltage and PIN CONFIGURATION differential thermal response, and they are suited for switching and ampli- fying applications in +1.0V to +10V (+/-5V) systems where low input bias current, low input capacitance and fast switching speed are desired. As ALD110808 these are MOSFET devices, they feature very large (almost infinite) cur- rent gain in a low frequency, or near DC, operating environment. - - V V IC* 1 16 IC* These devices are suitable for use in precision applications which require G 2 15 G very high current gain, beta, such as current mirrors and current sources. N1 N2 M 1 M 2 The high input impedance and the high DC current gain of the Field Effect 3 14 D D N2 N1 Transistors result from extremely low current loss through the control gate. + + The DC current gain is limited by the gate input leakage current, which is S 13 4 V V 12 specified at 30pA at room temperature. For example, DC beta of the - - 5 V 12 S V device at a drain current of 3mA and input leakage current of 30pA at 34 25C is = 3mA/30pA = 100,000,000. D 6 11 D N4 N3 M 4 M 3 G 7 10 N4 G N3 FEATURES IC* 8 9 IC* - - V Enhancement-mode (normally off) V Standard Gate Threshold Voltages: +0.80V Matched MOSFET to MOSFET characteristics SCL, PCL PACKAGES Tight lot to lot parametric control Low input capacitance ALD110908 V match to 2mV and 10mV GS(th) 12 High input impedance 10 typical - - V V Positive, zero, and negative V temperature coefficient GS(th) IC* 1 8 IC* 8 DC current gain >10 Low input and output leakage currents G 2 7 G N2 N1 M 1 M 2 D 3 D 6 N1 N2 ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) - - V S 4 V 5 12 Operating Temperature Range* 0C to +70C0C to +70C 16-Pin 16-Pin 8-Pin 8-Pin SAL, PAL PACKAGES SOIC Plastic Dip SOIC Plastic Dip Package Package Package Package *IC pins are internally connected. Connect to V- ALD110808ASCL ALD110808APCL ALD110908ASAL ALD110908APAL ALD110808SCL ALD110808PCL ALD110908SAL ALD110908PAL * Contact factory for industrial temp. range or user-specified threshold voltage values. 2016 Advanced Linear Devices, Inc., Vers. 2.3 www.aldinc.com 1 of 12 E N A D E L BABSOLUTE MAXIMUM RATINGS Drain-Source voltage, V 10.6V DS Gate-Source voltage, V 10.6V GS Power dissipation 500 mW Operating temperature range SCL, PCL, SAL, PAL 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS + - V = +5V V = GND T = 25C unless otherwise specified A ALD110808A/ALD110908A ALD110808/ALD110908 Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions Gate Threshold Voltage V 0.78 0.80 0.82 0.78 0.80 0.82 V I =1A, V = 0.1V GS(th) DS DS Offset Voltage V 12 3 10mV OS V -V GS(th)1 GS(th)2 Offset Voltage Tempco TC 55 V/CV = V VOS DS1 DS2 Gate Threshold Voltage TC -1.7 -1.7 mV/CI = 1A, V = 0.1V VGS(th) DS DS Tempco 0.0 0.0 I = 20A, V = 0.1V DS DS +1.6 +1.6 I = 40A, V = 0.1V DS DS Drain Source On Current I 12.0 12.0 mA V = +10.3V, V = +5V DS(ON) GS DS 3.0 3.0 V = +4.8V, V = +5V GS DS Forward Transconductance G 1.4 1.4 mmho V = +4.8V FS GS V = +9.8V DS Transconductance Mismatch G 1.8 1.8 % FS Output Conductance G 68 68 mho V = +4.8V OS GS V = +9.8V DS Drain Source On Resistance R 500 500 V = +4.8V DS(ON) GS V = +0.1V DS Drain Source On Resistance R 0.5 0.5 % DS(ON) Mismatch - Drain Source Breakdown BV 10 10 V V = V = -1.0V DSX GS Voltage I = 1.0A DS 1 Drain Source Leakage Current I 10 400 10 400 pA V = -0.2V, V = +5V DS(OFF) GS DS - V = -5V 44nAT = 125C A 1 Gate Leakage Current I 3 200 3 200 pA V = +5V, V = 0V GSS GS DS 11nAT =125C A Input Capacitance C 2.5 2.5 pF ISS Transfer Reverse Capacitance C 0.1 0.1 pF RSS + Turn-on Delay Time t 10 10 ns V = 5V, R = 5K on L + Turn-off Delay Time t 10 10 ns V = 5V, R = 5K off L Crosstalk 60 60 dB f = 100KHz 1 Notes: Consists of junction leakage currents ALD110808A/ALD110808/ Advanced Linear Devices 2 of 12 ALD110908A/ALD110908, Vers. 2.3