e TM ADVANCED EPAD LINEAR DEVICES, INC. ALD110814/ALD110914 QUAD/DUAL N-CHANNEL ENHANCEMENT MODE EPAD V = +1.40V GS(th) PRECISION MATCHED PAIR MOSFET ARRAY APPLICATIONS GENERAL DESCRIPTION Precision current mirrors ALD110814/ALD110914 are high precision monolithic quad/dual enhance- Precision current sources ment mode N-Channel MOSFETs matched at the factory using ALDs Voltage choppers proven EPAD CMOS technology. These devices are intended for low Differential amplifier input stages voltage, small signal applications. Discrete voltage comparators Voltage bias circuits The ALD110814/ALD110914 MOSFETs are designed and built with ex- Sample and Hold circuits ceptional device electrical characteristics matching. Since these devices Analog inverters are on the same monolithic chip, they also exhibit excellent tempco track- ing characteristics. Each device is versatile as a circuit element and is a Level shifters Source followers and buffers useful design component for a broad range of analog applications. They Current multipliers are basic building blocks for current sources, differential amplifier input Discrete analog multiplexers/matrices stages, transmission gates, and multiplexer applications. For most appli- Discrete analog switches cations, connect the V+ pin to the most positive voltage and the V- and IC pins to the most negative voltage in the system. All other pins must have voltages within these voltage limits at all times. The ALD110814/ALD110914 devices are built for minimum offset voltage and differential thermal response, and they are designed for switching PIN CONFIGURATION and amplifying applications in +1.5V to +10V systems where low input bias current, low input capacitance and fast switching speed are desired. Since these are MOSFET devices, they feature very large (almost infinite) ALD110814 current gain in a low frequency, or near DC, operating environment. - - V V IC* 1 16 IC* The ALD110814/ALD110914 are suitable for use in precision applications which require very high current gain, beta, such as current mirrors and 15 G G 2 N1 N2 current sources. The high input impedance and the high DC current gain M 2 M 1 of the Field Effect Transistors result in extremely low current loss through 14 D D 3 N1 N2 the control gate. The DC current gain is limited by the gate input leakage + + S 4 13 V 12 V current, which is specified at 30pA at room temperature. For example, DC beta of the device at a drain current of 3mA and input leakage current of - - V 5 V 12 S 34 30pA at 25C is 3mA/30pA = 100,000,000. D 6 11 D N4 M 4 N3 M 3 FEATURES G 7 10 N4 G N3 Enhancement-mode (normally off) IC* 8 9 IC* - - Standard Gate Threshold Voltages: +1.40V V V Matched MOSFET-to-MOSFET characteristics SCL, PCL PACKAGES Tight lot-to-lot parametric control Parallel connection of MOSFETs to increase drain currents ALD110914 Low input capacitance V match to 10mV GS(th) 12 - High input impedance 10 typical - V V 1 8 Positive, zero, and negative V temperature coefficient IC* GS(th) IC* 8 DC current gain >10 Low input and output leakage currents 7 G G 2 N1 N2 M 1 M 2 ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) D 3 D 6 N1 N2 Operating Temperature Range* - - S V 4 V 5 12 0C to +70C0C to +70C 16-Pin 16-Pin 8-Pin 8-Pin SAL, PAL PACKAGES SOIC Plastic Dip SOIC Plastic Dip Package Package Package Package *IC pins are internally connected. Connect to V- ALD110814SCL ALD110814PCL ALD110914SAL ALD110914PAL * Contact factory for industrial temp. range or user-specified threshold voltage values. 2016 Advanced Linear Devices, Inc., Vers. 2.3 www.aldinc.com 1 of 12 E N A D E L BABSOLUTE MAXIMUM RATINGS Drain-Source voltage, V 10.6V DS Gate-Source voltage, V 10.6V GS Power dissipation 500 mW Operating temperature range SCL, PCL, SAL, PAL 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS + - V = +5V V = GND T = 25C unless otherwise specified A ALD110814/ALD110914 Parameter Symbol Min Typ Max Unit Test Conditions Gate Threshold Voltage V 1.38 1.40 1.42 V I = 1A, V = 0.1V GS(th) DS DS Offset Voltage V 310 mVI = 1A OS DS V -V GS(th)1 GS(th)2 Offset VoltageTempco TC 5 V/CV = V VOS DS1 DS2 Gate Threshold Voltage TC -1.7 mV/CI = 1A, V = 0.1V VGS(th) DS DS Tempco 0.0 I = 20A, V = 0.1V DS DS +1.6 I = 40A, V = 0.1V DS DS Drain Source On Current I 12.0 mA V = +10.6V, V = +5V DS(ON) GS DS 3.0 V = +5.4V, V = +5V GS DS Forward Transconductance G 1.4 mmho V = +5.4V FS GS V = +10.4V DS Transconductance Mismatch G 1.8 % FS Output Conductance G 68 mho V = +5.4V OS GS V = +10.4V DS Drain Source On Resistance R 500 V = +5.4V DS(ON) GS V = +0.1V DS Drain Source On Resistance R 0.5 % DS(ON) Mismatch - Drain Source Breakdown BV 10 V V = V = -0.6V DSX GS Voltage I = 1.0A DS 1 Drain Source Leakage Current I 10 400 pA V = -0.6V, V =+5V DS(OFF) GS DS - V = -5V 4nA T = 125C A 1 Gate Leakage Current I 3 200 pA V = +5V, V = 0V GSS GS DS 1nA T =125C A Input Capacitance C 2.5 pF ISS Transfer Reverse Capacitance C 0.1 pF RSS + Turn-on Delay Time t 10 ns V = 5V, R = 5K on L + Turn-off Delay Time t 10 ns V = 5V, R = 5K off L Crosstalk 60 dB f = 100KHz 1 Notes: Consists of junction leakage currents ALD110814/ALD110914, Vers. 2.3 Advanced Linear Devices 2 of 12