e TM ADVANCED EPAD LINEAR DEVICES, INC. ALD210808A/ALD210808 PRECISION N-CHANNEL EPAD MOSFET ARRAY V = +0.80V GS(th) QUAD HIGH DRIVE MATCHED PAIR FEATURES & BENEFITS GENERAL DESCRIPTION + The ALD210808A/ALD210808 precision enhancement mode N-Channel EPAD Precision V = +0.80V 0.010V GS(th) V (V match) to 2mV/10mV max. MOSFET array is precision matched at the factory using ALDs proven EPAD OS GS(th) Sub-threshold voltage (nano-power) operation CMOS technology. These quad monolithic devices are enhanced additions to < 800mV min. operating voltage the ALD110808A/ALD110808 EPAD MOSFET Family, with increased forward transconductance and output conductance, particularly at very low supply volt- < 1nA min. operating current < 1nW min. operating power ages. > 100,000,000:1 operating current ranges High transconductance and output conductance Intended for low voltage, low power small signal applications, the ALD210808A/ ALD210808 features precision threshold voltage, which enables circuit designs Low R of 25 DS(ON) with input/output signals referenced to GND at enhanced operating voltage Output current > 50mA ranges. With these devices, a circuit with multiple cascading stages can be Matched and tracked tempco Tight lot-to-lot parametric control built to operate at extremely low supply/bias voltage levels. For example, a nanopower input amplifier stage operating at less than 1.0V supply voltage has Positive, zero, and negative V tempco GS(th) been successfully built with these devices. Low input capacitance and leakage currents ALD210808A EPAD MOSFETs feature exceptional matched pair electrical char- APPLICATIONS + acteristics of Gate Threshold Voltage V set precisely at +0.80V 0.01V, GS(th) + I = +10A V = 0.1V, with a typical offset voltage of only 0.001V (1mV). DS DS Low overhead current mirrors and current sources Built on a single monolithic chip, they also exhibit excellent temperature track- Zero Power Normally-On circuits ing characteristics. These precision devices are versatile as design components Energy harvesting detectors for a broad range of analog small signal applications such as basic building Very low voltage analog and digital circuits blocks for current mirrors, matching circuits, current sources, differential ampli- Zero power fail-safe circuits fier input stages, transmission gates, and multiplexers. They also excel in lim- Backup battery circuits & power failure detector ited operating voltage applications, such as very low level voltage-clamps and Extremely low level voltage-clamps nano-power normally-on circuits. Extremely low level zero-crossing detectors Matched source followers and buffers In addition to precision matched-pair electrical characteristics, each individual Precision current mirrors and current sources EPAD MOSFET also exhibits well controlled manufacturing characteristics, en- Matched capacitive probes and sensor interfaces abling the user to depend on tight design limits from different production batches. Charge detectors and charge integrators These devices are built for minimum offset voltage and differential thermal re- High gain differential amplifier input stage sponse, and they can be used for switching and amplifying applications in +0.1V Matched peak-detectors and level-shifters + + to +10V ( 0.05V to 5V) powered systems where low input bias current, low Multiple Channel Sample-and-Hold switches input capacitance, and fast switching speed are desired. At V > +0.80V, the GS Precision Current multipliers device exhibits enhancement mode characteristics whereas at V < +0.80V GS Discrete matched analog switches/multiplexers the device operates in the subthreshold voltage region and exhibits conven- Nanopower discrete voltage comparators tional sub threshold characteristics, with well controlled turn-off and sub-thresh- old levels that operate the same as standard enhancement mode MOSFETs. PIN CONFIGURATION 10 The ALD210808A/ALD210808 features high input impedance (2.5 x 10 ) and 8 high DC current gain (>10 ). A sample calculation of the DC current gain at a drain output current of 30mA and input current of 300pA at 25C is 30mA/300pA ALD210808 = 100,000,000, which translates into a dynamic operating current range of about eight orders of magnitude. A series of four graphs titled Forward Transfer Char- nd rd acteristics, with the 2 and 3 sub-titled expanded (subthreshold) and fur- 1 IC* 16 IC* th ther expanded (subthreshold), and the 4 sub-titled low voltage, illustrates M 1 M 2 the wide dynamic operating range of these devices. D N1 2 15 D N2 Generally it is recommended that the V+ pin be connected to the most positive G N1 3 14 G N2 voltage and the V- and IC (internally-connected) pins to the most negative volt- - - age in the system. All other pins must have voltages within these voltage limits V V 4 S 13 S at all times. Standard ESD protection facilities and handling procedures for static N1 N2 sensitive devices are highly recommended when using these devices. - - + + V 12 V 5 V V M 4 M 3 ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) D N4 6 11 D N3 Operating Temperature Range * G N4 7 10 G N3 0C to +70C - - V V 16-Pin SOIC Package 16-Pin Plastic Dip Package S 8 9 S N4 N3 ALD210808ASCL ALD210808APCL ALD210808SCL ALD210808PCL SCL, PCL PACKAGES *IC pins are internally connected, connect to V- *Contact factory for industrial temp. range or user-specified threshold voltage values. 2019 Advanced Linear Devices, Inc., Vers. 1.3 www.aldinc.com 1 of 12 E N A D E L BABSOLUTE MAXIMUM RATINGS Drain-Source voltage, V 10.0V DS Gate-Source voltage, V 10.0V GS Operating Current 80mA Power dissipation 500mW Operating temperature range SCL, PCL 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS + - V = +5V V = GND T = 25C unless otherwise specified A ALD210808A ALD210808 Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions Gate Threshold Voltage V 0.78 0.80 0.82 0.78 0.80 0.82 V I = 10A, V = 0.1V GS(th) DS DS Offset Voltage V 1 2 2 10 mV V - V OS GS(th)M1 GS(th)M2 or V - V GS(th)M3 GS(th)M4 Offset Voltage Tempco TC 55 V/CV = V VOS DS1 DS2 Gate Threshold Voltage Tempco TC -1.6 -1.6 mV/CI = 10A, V = 0.1V VGS(th) D DS 0.0 0.0 I = 380A, V = 0.1V D DS +1.6 +1.6 I = 700A, V = 0.1V D DS 70 70 mA V = +4.8V, V = +5V Drain Source On Current I GS DS DS(ON) 50 50 AV = +0.9V, V = +0.1V GS DS Forward Transconductance G 24 24 mmho V = +4.8V FS GS V = +5.0V DS Transconductance Mismatch G 1.8 1.8 % FS Output Conductance G 1.6 1.6 mmho V = +4.8V OS GS V = +5.0V DS Drain Source On Resistance R 25 25 V = +5.8V DS(ON) GS V = +0.1V DS Drain Source On Resistance R 10 10 K V = +0.8V, V = +0.1V DS(ON) GS DS 2.0 2.0 V = +0.9V, V = +0.1V GS DS Drain Source On Resistance R 1.8 1.8 % V = +5.8V DS(ON) GS Tolerance V = +0.1V DS Drain Source On Resistance R 0.6 0.6 % DS(ON) Mismatch - Drain Source Breakdown BV 10 10 V V = V = -0.2V DSX GS Voltage I = 10A DS 1 Drain Source Leakage Current I 10 400 10 400 pA V = -0.2V, V = +5V DS(OFF) GS DS - V = -5V 44nAT = 125C A 1 Gate Leakage Current I 5 200 5 200 pA V = +5V, V = 0V GSS GS DS 11nAT = 125C A Input Capacitance C 15 15 pF ISS Transfer Reverse Capacitance C 11 pF RSS + Turn-on Delay Time t 10 10 ns V = 5V, R = 5K on L + Turn-off Delay Time t 10 10 ns V = 5V, R = 5K off L Crosstalk 60 60 dB f = 100KHz 1 Notes: Consists of junction leakage currents ALD210808A/ALD210808 Advanced Linear Devices 2 of 12