e TM ADVANCED EPAD LINEAR DEVICES, INC. ALD310702A/ALD310702 PRECISION P-CHANNEL EPAD MOSFET ARRAY V = -0.20V QUAD NANOPOWER MATCHED PAIR GS(th) APPLICATIONS GENERAL DESCRIPTION 0.5% precision current mirrors and current sources ALD310702A/ALD310702 high precision monolithic quad P-Channel Low Tempco (<= 50ppm/C) current mirrors/sources MOSFET arrays are matched at the factory using ALD s proven EPAD Energy harvesting circuits CMOS technology. This device is available in a quad version and is a Very low voltage analog and digital circuits member of the EPAD Matched Pair MOSFET Family. The Backup battery circuits & power failure detectors ALD310702A/ALD310702 is a P-channel version of the popular Precision low level voltage-clamps ALD110802A/ALD110802 Precision Threshold device. Together, these Low level zero-crossing detector two MOSFET series enable complementary precision N-Channel and P- Source followers and buffers Channel MOSFET array based circuits. Precision capacitive probes and sensor interfaces Precision charge detectors and charge integrators Intended for low voltage and low power small signal applications, the Discrete differential amplifier input stage ALD310702A/ALD310702 features precision -0.20V Gate Threshold Peak-detectors and level-shifters Voltage, which enables circuit designs with very low operating voltages High-side switches and Sample-and-Hold switches such as < +0.5V power supplies where the circuits operate below the Precision current multipliers threshold voltage of the ALD310702A/ALD310702. This feature also Discrete analog switches / multiplexers enhances input/output signal operating ranges, especially in very low Discrete voltage comparators operating voltage environments. With these low threshold precision devices, a circuit with multiple cascading stages can be constructed to operate at extremely low supply or bias voltage levels. ALD310702A/ FEATURES & BENEFITS 10 ALD310702 also features high input impedance (2.5 x 10 ) and high Precision matched Gate Threshold Voltages 8 DC current gain (>10 ). Precision offset voltages (V ): OS ALD310702A: 1mV typical ALD310702A/ALD310702 MOSFETs are designed for exceptional ALD310702: 2mV typical matching of device electrical characteristics. The Gate Threshold Voltage Sub-threshold voltage operation +/- V is set precisely at -0.20V 0.02V, featuring a typical offset GS(th) Low min. operating voltage of less than 0.2V +/- voltage of only 0.001V (1mV). As these devices are on the same Ultra low min. operating current of less than 1nA monolithic chip, they also exhibit excellent temperature tracking Nano-power operation characteristics. They are versatile design components for a broad range Wide dynamic operating current ranges of precision analog applications such as basic building blocks for current Exponential operating current ranges mirrors, matching circuits, current sources, differential amplifier input Matched transconductance and output conductance stages, transmission gates, and multiplexers. These devices also excel Matched and tracked temperature characteristics in limited operating voltage applications such as very low level precision Tight lot-to-lot parametric control voltage-clamps. In addition to matched pair electrical characteristics, Positive, zero, and negative V tempco bias currents GS(th) each individual MOSFET exhibits individual well controlled manufacturing Low input capacitance characteristics, enabling the user to depend on tight design limits from Low input/output leakage currents different production batches. (Continued on next page) PIN CONFIGURATION BLOCK DIAGRAM ALD310702 - V (5) I * 1 16 C1 I * C2 D (15) D (6) D (2) P2 ~ D (11) M1 M2 P1 P3 P4 D 2 15 P1 D P2 G (3) G (14) G (10) G (7) G G P1 P2 P3 P4 3 14 P1 P2 I (1) I (16) C1 C2 S S + P1 4 13 P2 + V (12) V (12) S (4) S (13) S (9) S (8) P1 P2 P3 P4 - - - + V V V V 5 12 M4 M3 D D 11 P4 6 P3 ORDERING INFORMATION (L suffix denotes lead-free (RoHS)) G G P4 7 P3 10 Operating Temperature Range * 0C to +70C S S P4 8 9 P3 16-Pin SOIC Package 16-Pin Plastic Dip Package ALD310702ASCL ALD310702APCL SCL, PCL PACKAGES ALD310702SCL ALD310702PCL *I pins are internally connected, connect to V- C *Contact factory for industrial temp. range or user-specified threshold voltage values. 2021 Advanced Linear Devices, Inc., Vers. 1.2 www.aldinc.com 1 of 9 E N A D E L BGENERAL DESCRIPTION (cont.) These devices are built to offer minimum offset voltage and differential or below the Gate Threshold Voltage (subthreshold region). Second, thermal response, and they can also be used for switching and the circuit can be biased and operated in the subthreshold region +/- +/- amplifying applications in -0.40V to -8.0V ( 0.20V to 4.0V) with nA of bias current and nW of power dissipation. powered systems where low input bias current, low input capacitance, and fast switching speed are desired. These devices, exhibiting well For most general applications, connect the V+ pin to the most controlled turn-off and sub-threshold characteristics, operate the positive voltage and the V- and IC (internally-connected) pins to the same as standard enhancement mode P-Channel MOSFETs. most negative voltage in the system. All other pins must have voltages within these voltage limits at all times. Standard ESD However, the precision of the Gate Threshold Voltage enable two key additional characteristics, or operating features. First, the protection facilities and procedures for static sensitive devices are operating current level varies exponentially with gate bias voltage at required when handling these devices. ABSOLUTE MAXIMUM RATINGS Drain-Source voltage, V -8.0V DS Gate-Source voltage, V -8.0V GS Operating Current 80mA Power dissipation 500mW Operating temperature range SCL, PCL 0C to +70C Storage temperature range -65C to +150C Lead temperature, 10 seconds +260C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. OPERATING ELECTRICAL CHARACTERISTICS + - V = +5V V = GND T = 25C unless otherwise specified A ALD310702A ALD310702 Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions Gate Threshold V -0.22 -0.20 -0.18 -0.22 -0.20 -0.18 V I = -1A, V = -0.1V GS(th) DS DS Voltage Offset Voltage V 1 5 2 20 mV V - V OS GS(th)M1 GS(th)M2 or V - V GS(th)M3 GS(th)M4 Gate Threshold TC -2 -2 mV/C VGS(th) Temperature Drain Source On I -2.03 -2.03 mA V = V = -5.0V DS(ON) GS DS Current Transconductance G 570 570 A/V V = V = -5.0V FS GS DS 2 Current Transconductance G 11 %V = V = -5.0V FS GS DS Mismatch 2 Output Conductance G 48 48 A/V V = -4.0V, OS GS(th) V = -5.0V DS Drain Source On R 1.14 1.14 K V = -5.0V, DS(ON) GS Resistance V = -0.1V DS Drain Source On R 11 % DS(ON) Resistance Mismatch Drain Source BV -8.0 -8.0 V DSX Breakdown Drain Source I 400 400 pA DS (OFF) 1 Leakage Current Gate Leakage Current I 200 200 pA GSS 2 Input Capacitance C 2.5 2.5 pF ISS 1 Notes: Consists of junction leakage currents 2 Sample tested parameters ALD310702A/ALD310702 Advanced Linear Devices, Inc. 2 of 9