DataSheet BCM53106S Multiport Ultra Low-Power Ethernet Switches GENERAL DESCRIPTION FEATURES The Broadcom BCM53106S is an ultra low-power, highly Four 10/100M and two 10/100/1000M media access integrated, cost-effective smart Fast Ethernet switch. The controllers switchdesignisbasedonthefield-proven,industry-leading Four-port 10/100 transceivers for TX ROBO architecture. This device combines all the functions One RGMII interface for an inband management port of a high-speed switch system including packet buffers, (IMP) for connection to a CPU/management entity PHY transceivers, media access controllers (MACs), without PHY address management, port-based rate control, and a One RGMII interface for a connection to another PHY, nonblockingswitchfabricintoasingle28nmCMOSdevice. CPU, or Modem. Designed to be fully compliant with the IEEE 802.3 and IEEE802.1p,MACPort,TOS,andDiffServQoSforsix IEEE 802.3x specifications, including the MAC-control queues, plus two time sensitive queues PAUSE frame, the BCM53106Sprovidescompatibility with Port-based VLAN all industry-standard Ethernet and Fast Ethernet devices. IEEE 802.1Q-based VLAN with 4K entries MAC-based trunking with automatic link failover TheBCM53106Shasarichfeaturesetsuitablefornotonly Port-based rate control standard Fast Ethernet connectivity for broadband home Port mirroring (Ingress/Egress) gateways, desktop and laptop PCs, but also for next- Supports IPv4 and IPv6 generation gaming consoles, set-top boxes, networked Priority modification on egress DVD players, and home theater receivers. It is also BroadSync HD for IEEE 802.1AS support specifically designed for next generation SOHO/SMB Timestamp tagging at MAC interface routers and gateways. Time-aware egress scheduler TheBCM53106Scontainsfourfull-duplex10/100BASE-TX DOS attack prevention Ethernettransceivers.Inaddition,theBCM53106Shastwo IGMP Snooping, MLD snooping support PHY-less interfaces for the CPU or a router chip, providing Spanning tree support (multiple spanning treesup to flexible10/100Mbpsconnectivity.OneRGMIIinterfacecan eight) be connected to a CPU entity and configured as an IMP (In Embedded CPU (8051) processor for cable Band Management port). diagnostics. CableChecker with unmanaged mode support The second RGMII interface is available for another PHY, Double tagging/QinQ Modem, or CPU connection. IEEE802.az Energy Efficient Ethernet (EEE) support The BCM53106S provides 70+ on-chip MIB counters to IEEE 802.3x programmable per-port flow control and collect receive and transmit statistics for each port. backpressure, with IEEE 802.1X support for secure The BCM53106S is available in industrial temperature (I- user authentication Temp) and commercial temperature (C-Temp) rated EEPROM, MDC/MDIO, and SPI Interface. packages. The BCM53106S is available in one package Serial Flash Interface for accessing embedded CPU type, a 212-pin FBGA package. (8051) 4K entry MAC address table with automatic learning and aging 128 KB packet buffer (1 KB = 1024 bytes) 128 multicast group support Jumbo frame support up to 9720 byte 1.0V for core and 3.3V for I/O RGMII with option of 2.5V or 1.5V JTAG support 212-pin FBGA package 53106S-DS103-R Corporate Headquarters: San Jose, CA September 12, 2016BCM53106S Data Sheet Revision History Figure 1: BCM53106S Functional Block Diagram TDP/N 0 1:0 10/100 PHY GMAC TDP/N 1 1:0 10/100 PHY GMAC Registers TDP/N 2 1:0 10/100 PHY GMAC Packet Buffer MMU TDP/N 3 1:0 10/100 PHY GMAC Address Management GMAC RGMII LED Interface LED 8051 Micro Flash Controller Memory RGMII GMAC EEPROM/ EEPROM/SPI CPU Interface Broadcom September 12, 2016 53106S-DS103-R Page 2 BROADCOM CONFIDENTIAL