STK12C68-M STK12C68-M CMOS nvSRAM 8K x 8 AutoStore Nonvolatile Static RAM MIL-STD-883 / SMD 5962-94599 FEATURES DESCRIPTION The Simtek STK12C68-M is a fast static RAM (40, 45 40, 45 and 55ns Access Times and 55ns), with a nonvolatile EEPROM element incor- 15 mA I at 200ns Access Speed CC porated in each static memory cell. The SRAM can be Automatic STORE to EEPROM on Power Down read and written an unlimited number of times, while Hardware or Software initiated STORE to independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the EEPROM STORE operation) take place automatically upon power Automatic STORE Timing down using charge stored in an external 100 F 100,000 STORE cycles to EEPROM capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on 10 year data retention in EEPROM power up. Software sequences may also be used to Automatic RECALL on Power Up initiate both STORE and RECALL operations. A Software initiated RECALL from EEPROM STORE can also be initiated via a single pin. Unlimited RECALL cycles from EEPROM The STK12C68-M is available in the following pack- Single 5V10% Operation ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC. Available in multiple standard packages LOGIC BLOCK DIAGRAM PIN CONFIGURATIONS V 1 28 V CAP CCX EEPROM ARRAY 2 27 W A 12 256 x 256 3 26 A HSB 7 32 28 27 A 1 A 4 25 A 3 6 8 A 4 26 HSB 6 STORE 5 24 A A 9 A 5 25 A 5 5 8 A 4 23 A 6 A A 6 24 A 4 11 4 9 A 7 A 22 G 7 23 5 RECALL A A 3 3 11 STATIC RAM 8 8 A 21 A A TOP VIEW 22 G 10 2 A 2 6 ARRAY 9 20 A 9 21 A A E 1 10 1 A 7 10 20 A 10 19 DQ 7 A E AA 0 0 256 x 256 0 12 19 11 18 DQ 11 DQ DQ DQ 6 0 7 A 0 8 12 18 DQ DQ 12 17 1 6 DQ DQ 5 1 13 14 15 16 17 A HSB 16 9 DQ 13 DQ 4 STORE/ 2 RECALL 14 15 V DQ 3 A SS 12 CONTROL 28 - 300 C-DIP 28 - LCC DQ 0 COLUMN I/O DQ PIN NAMES 1 A - A Address Inputs DQ 2 0 12 COLUMN DECODER W Write Enable DQ3 DQ - DQ Data In/Out 0 7 DQ4 E Chip Enable DQ 5 AA A A A 0112 101 G G Output Enable DQ6 V Power (+5V) CCX DQ7 V Ground SS E V Capacitor CAP W HSB Hardware Store/Busy 4-53 INPUT BUFFERS ROW DECODER DQ A 2 7 Vss A 12 DQ V 3 CAP DQ V 4 CCX DQ W 5STK12C68-M a ABSOLUTE MAXIMUM RATINGS Voltage on typical input relative to V . 0.6V to 7.0V Note a: Stresses greater than those listed underAbsolute Maximum SS Voltage on DQ and G .0.5V to (V +0.5V) Rating may cause permanent damage to the device. This is a stress 0-7 CC Temperature under bias 55C to 125C rating only, and functional operation of the device at conditions above Storage temperature . 65C to 150C those indicated in the operational sections of this specification is not Power dissipation 1W implied. Exposure to absolute maximum rating conditions for extended DC output current .15mA periods may affect reliability. (One output at a time, one second duration) d DC CHARACTERISTICS (V = 5.0V 10%) CC SYMBOL PARAMETER MIN MAX UNITS NOTES b I Average V Current 85 mA t = 40ns CC CC AVAV 1 80 mA t = 45ns AVAV 75 mA t = 55ns AVAV I Average V Current During STORE 8 mA All inputs 0.2V or (V 0.2V) CC CC CC 2 b I Average V Current 15 mA E 0.2V, W (V 0.2V) CC CC CC 3 at t = 200ns others 0.2V or (V 0.2V) AVAV CC I Average VCC current during AutoStore cycle 4 mA All inputs 0.2V or (V - 0.2V) CC CC 4 c I Average V Current 35 mA t = 40ns SB CC AVAV 1 (Standby, Cycling TTL Input Levels) 32 mA t = 45ns AVAV 28 mA t = 55ns AVAV E V all others cycling IH b I Average V Current 4 mA E (V 0.2V) CC CC CC 2 (Standby, Stable CMOS Input Levels) I Input Leakage Current (Any Input) 1 AV = max ILK CC V = V to V IN SS CC I Off State Output Leakage Current 5 AV = max OLK CC V = V to V OUT SS CC V Input Logic1 Voltage 2.2 V +.5 V All Inputs IH CC V Input Logic0 Voltage V .5 0.8 V All Inputs IL SS V Output Logic1 Voltage 2.4 V I = 4mA except HSB OH OUT V Output Logic0 Voltage 0.4 V I = 8mA except HSB OL OUT T Operating Temperature 55 125 C A Note b: I and I are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. CC CC 1 3 Note c: Bringing E V will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. IH Note d: V reference levels throughout this datasheet refer to V if that is where the power supply connection is made, or V if V is connected to ground. CC CCX CAP CCX AC TEST CONDITIONS 5.0V Input Pulse Levels . V to 3V SS Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V 480 Ohms Output Load . See Figure 1 Output 30pF CAPACITANCE (T =25C, f=1.0MHz) A INCLUDING 255 Ohms SCOPE AND FIXTURE SYMBOL PARAMETER MAX UNITS CONDITIONS C Input Capacitance 8 pF V = 0 to 3V IN C Output Capacitance 7 pF V = 0 to 3V OUT Figure 1: AC Output Loading 4-54