Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14C101J CY14B101J CY14E101J 2 1-Mbit (128K 8) Serial (I C) nvSRAM 1-Mbit (128K 8) Serial (I2C) nvSRAM Sleep mode current of 8 A Features Industry standard configurations 1-Mbit nonvolatile static random access memory (nvSRAM) Operating voltages: Internally organized as 128K 8 CY14C101J: V = 2.4 V to 2.6 V CC STORE to QuantumTrap nonvolatile elements initiated CY14B101J: V = 2.7 V to 3.6 V 2 CC automatically on power-down (AutoStore) or by using I C CY14E101J: V = 4.5 V to 5.5 V CC command (Software STORE) or HSB pin (Hardware STORE) Industrial temperature RECALL to SRAM initiated on power-up (Power-Up 2 8- and 16-pin small outline integrated circuit (SOIC) package RECALL) or by I C command (Software RECALL) Restriction of hazardous substances (RoHS) compliant Automatic STORE on power-down with a small capacitor (except for CY14X101J1) Functional Description High reliability The Cypress CY14C101J/CY14B101J/CY14E101J combines a Infinite read, write, and RECALL cycles 2 1-Mbit nvSRAM with a nonvolatile element in each memory 1 million STORE cycles to QuantumTrap cell. The memory is organized as 128K words of 8 bits each. The Data retention: 20 years at 85 C embedded nonvolatile elements incorporate the QuantumTrap 2 1 High speed I C interface technology, creating the worlds most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while Industry standard 100 kHz and 400 kHz speed the QuantumTrap cells provide highly reliable nonvolatile Fast-mode Plus: 1 MHz speed storage of data. Data transfers from SRAM to the nonvolatile High speed: 3.4 MHz elements (STORE operation) takes place automatically at Zero cycle delay reads and writes power-down (except for CY14X101J1). On power-up, data is Write protection restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be Hardware protection using Write Protect (WP) pin 2 initiated by the user through I C commands. Software block protection for 1/4, 1/2, or entire array 2 For a complete list of related documentation, click here. I C access to special functions Nonvolatile STORE/RECALL Configuration 8 byte serial number Feature CY14X101J1 CY14X101J2 CY14X101J3 Manufacturer ID and Product ID Sleep mode AutoStore No Yes Yes Low power consumption Software STORE Yes Yes Yes Average active current of 1 mA at 3.4 MHz operation Hardware STORE No No Yes Average standby mode current of 150 A Logic Block Diagram Serial Number 8 x 8 V V CC CAP Manufacturer ID / Product ID Power Control Memory Control Register Block Command Register Quantum Trap 128 K x 8 Sleep STORE SRAM Control Registers Slave SDA 2 Memory 128 K x 8 I C Control Logic RECALL SCL Memory Slave Slave Address Address and Data A2, A1 Decoder Control WP Notes 2 1. The I C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips which support only one mode of operation. Refer to AN87209 for more details. 2 2. Serial (I C) nvSRAM is referred to as nvSRAM throughout the datasheet. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-54050 Rev. *P Revised August 7, 2018