Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14B101LA CY14B101NA 1-Mbit (128 K 8/64 K 16) nvSRAM CY14B101LA/CY14B101NA, 1-Mbit (128 K 8/64 K 16) nvSRAM Packages Features 32-pin small-outline integrated circuit (SOIC) 20 ns, 25 ns, and 45 ns access times 44-/54-pin thin small outline package (TSOP) Type II 48-pin shrink small-outline package (SSOP) Internally organized as 128 K 8 (CY14B101LA) or 64 K 16 48-ball fine-pitch ball grid array (FBGA) (CY14B101NA) Pb-free and restriction of hazardous substances (RoHS) Hands off automatic STORE on power-down with only a small compliant capacitor STORE to QuantumTrap nonvolatile elements initiated by Functional Description software, device pin, or AutoStore on power-down The Cypress CY14B101LA/CY14B101NA is a fast static RAM RECALL to SRAM initiated by software or power-up (SRAM), with a nonvolatile element in each memory cell. The Infinite read, write, and RECALL cycles memory is organized as 128 K bytes of 8 bits each or 64 K words of 16 bits each. The embedded nonvolatile elements incorporate 1 million STORE cycles to QuantumTrap QuantumTrap technology, producing the worlds most reliable 20 year data retention nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly Single 3 V +20% to 10% operation reliable QuantumTrap cell. Data transfers from the SRAM to the Industrial temperature nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. For a complete list of related resources, click here. 1, 2, 3 Logic Block Diagram V V CC CAP Quatrum Trap 1024 X 1024 R A POWER 5 O A CONTROL STORE 6 W A 7 RECALL A 8 D STORE/RECALL A E 9 HSB CONTROL STATIC RAM A C 12 ARRAY A 13 O 1024 X 1024 A D 14 SOFTWARE A E A - A 15 14 2 DETECT A R 16 DQ 0 DQ 1 DQ 2 DQ 3 I DQ 4 N DQ 5 P U DQ 6 T DQ 7 B COLUMN I/O U DQ 8 F DQ F 9 E OE DQ 10 COLUMN DEC R WE DQ 11 S DQ 12 DQ 13 CE DQ 14 BLE A A A A A A A 0 1 2 3 4 10 11 DQ 15 BHE Notes 1. Address A A for 8 configuration and Address A A for 16 configuration. 0 16 0 15 2. Data DQ DQ for 8 configuration and Data DQ DQ for 16 configuration. 0 7 0 15 3. BHE and BLE are applicable for 16 configuration only. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-42879 Rev. *S Revised April 24, 2020