CY14B101LA
CY14B101NA
1-Mbit (128 K 8/64 K 16) nvSRAM
1-Mbit (128 K 8/64 K 16) nvSRAM
Packages
Features
32-pin small-outline integrated circuit (SOIC)
20 ns, 25 ns, and 45 ns access times
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small-outline package (SSOP)
Internally organized as 128 K 8 (CY14B101LA) or 64 K 16
48-ball fine-pitch ball grid array (FBGA)
(CY14B101NA)
Pb-free and restriction of hazardous substances (RoHS)
Hands off automatic STORE on power-down with only a small
compliant
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
Functional Description
software, device pin, or AutoStore on power-down
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
RECALL to SRAM initiated by software or power-up
(SRAM), with a nonvolatile element in each memory cell. The
Infinite read, write, and RECALL cycles
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
1 million STORE cycles to QuantumTrap
QuantumTrap technology, producing the worlds most reliable
20 year data retention
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
Single 3 V +20% to 10% operation
reliable QuantumTrap cell. Data transfers from the SRAM to the
Industrial temperature
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related resources, click here.
[1, 2, 3]
Logic Block Diagram
V V
CC CAP
Quatrum Trap
1024 X 1024
R
A POWER
5
O
CONTROL
A STORE
6
W
A
7
RECALL
A
D
8
STORE/RECALL
A
E
9 HSB
CONTROL
A STATIC RAM
C
12
A ARRAY
O
13
1024 X 1024
A D
14
SOFTWARE
A E A - A
15 14 2
DETECT
A R
16
DQ
0
DQ
1
DQ
2
DQ
3
I
DQ
4
N
DQ
5 P
U
DQ
6
T
DQ
7 B COLUMN I/O
U
DQ
8
F
DQ F
9
OE
E
DQ
10
COLUMN DEC
R
WE
DQ
11 S
DQ
12
DQ
13
CE
DQ
14
BLE
A A A A A A A
2
0 1 3 4 10 11
DQ
15
BHE
Notes
1. Address A A for 8 configuration and Address A A for 16 configuration.
0 16 0 15
2. Data DQ DQ for 8 configuration and Data DQ DQ for 16 configuration.
0 7 0 15
3. BHE and BLE are applicable for 16 configuration only.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-42879 Rev. *Q Revised November 12, 2014CY14B101LA
CY14B101NA
Contents
Pinouts ..............................................................................3 Switching Waveforms .................................................... 12
Pin Definitions ..................................................................5 AutoStore/Power-Up RECALL ....................................... 15
Device Operation ..............................................................6 Switching Waveforms .................................................... 15
SRAM Read ................................................................6 Software Controlled STORE/RECALL Cycle ................ 16
SRAM Write .................................................................6 Switching Waveforms .................................................... 16
AutoStore Operation ....................................................6 Hardware STORE Cycle ................................................. 17
Hardware STORE Operation .......................................6 Switching Waveforms .................................................... 17
Hardware RECALL (Power-up) ...................................7 Truth Table For SRAM Operations ................................ 18
Software STORE .........................................................7 Ordering Information ...................................................... 19
Software RECALL .......................................................7 Ordering Code Definitions ......................................... 20
Preventing AutoStore ..................................................8 Package Diagrams .......................................................... 21
Data Protection ............................................................8 Acronyms ........................................................................26
Maximum Ratings .............................................................9 Document Conventions ................................................. 26
Operating Range ...............................................................9 Units of Measure ....................................................... 26
DC Electrical Characteristics ..........................................9 Document History Page ................................................. 27
Data Retention and Endurance .....................................10 Sales, Solutions, and Legal Information ...................... 30
Capacitance ....................................................................10 Worldwide Sales and Design Support ....................... 30
Thermal Resistance ........................................................10 Products ....................................................................30
AC Test Loads ................................................................11 PSoC Solutions ......................................................... 30
AC Test Conditions ........................................................11
AC Switching Characteristics .......................................12
SRAM Read Cycle ....................................................12
SRAM Write Cycle .....................................................12
Document Number: 001-42879 Rev. *Q Page 2 of 30