Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY14B101Q1 CY14B101Q2 CY14B101Q3 1-Mbit (128K 8) Serial SPI nvSRAM 1-Mbit (128K 8) Serial SPI nvSRAM CY14B101Q1 has identical pin configuration to industry Features standard 8-pin NV memory 8-pin dual flat no-lead (DFN) package and 16-pin small 1-Mbit nonvolatile static random access memory (nvSRAM) outline integrated circuit (SOIC) package Internally organized as 128K 8 Restriction of hazardous substances (RoHS) compliant STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using Functional Description HSB pin (Hardware STORE) or SPI instruction (Software STORE) The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3 RECALL to SRAM initiated on power-up (Power-Up combines a 1-Mbit nvSRAM with a nonvolatile element in each RECALL) or by SPI instruction (Software RECALL) memory cell with serial SPI interface. The memory is organized Automatic STORE on power-down with a small capacitor as 128 K words of 8 bits each. The embedded nonvolatile (except for CY14B101Q1) elements incorporate the QuantumTrap technology, creating the High reliability worlds most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cell Infinite read, write, and RECALL cycles provides highly reliable nonvolatile storage of data. Data 1 million STORE cycles to QuantumTrap transfers from SRAM to the nonvolatile elements (STORE Data retention: 20 years operation) takes place automatically at power-down (except for High speed serial peripheral interface (SPI) CY14B101Q1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). Both STORE and 40 MHz clock rate RECALL operations can also be initiated by the user through SPI Supports SPI mode 0 (0, 0) and mode 3 (1, 1) instruction. Write protection For a complete list of related documentation, click here. Hardware protection using Write Protect (WP) pin Software protection using Write Disable instruction Configuration Software block protection for 1/4,1/2, or entire array Feature CY14B101Q1 CY14B101Q2 CY14B101Q3 Low power consumption AutoStore No Yes Yes Single 3 V +20%, 10% operation Software Yes Yes Yes Average active current of 10 mA at 40 MHz operation STORE Industry standard configurations Hardware No No Yes Industrial temperature STORE Logic Block Diagram V V CC CAP QuantumTrap Power Control 128 K X 8 CS Instruction decode WP Write protect Control logic SCK STORE/RECALL STORE SRAM Array HSB Control HOLD RECALL 128 K X 8 Instruction D0-D7 register A0-A16 Address Decoder Data I/O register SO SI Status Register Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-50091 Rev. *P Revised January 12, 2018