CY14B101Q1 CY14B101Q2 CY14B101Q3 1 Mbit (128K x 8) Serial SPI nvSRAM Features Functional Overview The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3 1 Mbit Nonvolatile SRAM combines a 1 Mbit nonvolatile static RAM with a nonvolatile Internally organized as 128K x 8 element in each memory cell. The memory is organized as 128K STORE to QuantumTrap Nonvolatile Elements initiated au- words of 8 bits each. The embedded nonvolatile elements incor- tomatically on Power Down (AutoStore) or by user using HSB porate the QuantumTrap technology, creating the worlds most Pin (Hardware Store) or SPI instruction (Software Store) reliable nonvolatile memory. The SRAM provides infinite read RECALL to SRAM initiated on Power Up (Power Up Recall) and write cycles, while the QuantumTrap cell provides highly or by SPI Instruction (Software RECALL) reliable nonvolatile storage of data. Data transfers from SRAM to Automatic STORE on Power Down with a small Capacitor the nonvolatile elements (STORE operation) takes place High Reliability automatically at power down. On power up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). Infinite Read, Write, and RECALL Cycles Both STORE and RECALL operations can also be triggered by 1 Million STORE cycles to QuantumTrap the user. Data Retention: 20 Years Configuration High Speed Serial Peripheral Interface (SPI) 40 MHz Clock Rate Feature CY14B101Q1 CY14B101Q2 CY14B101Q3 Supports SPI Modes 0 (0,0) and 3 (1,1) AutoStore No Yes Yes Write Protection Software Yes Yes Yes Hardware Protection using Write Protect (WP) Pin STORE Software Protection using Write Disable Instruction Hardware No No Yes Software Block Protection for 1/4,1/2, or entire Array STORE Low Power Consumption Single 3V +20%, 10% Operation Average V current of 10 mA at 40 MHz Operation CC Industry Standard Configurations Industrial Temperature CY14B101Q1 has identical pin configuration to industry stan- dard 8-pin NV Memory 8-pin DFN and 16-pin SOIC Packages RoHS Compliant V V Logic Block Diagram CC CAP Quantum Trap Power Control 128K X 8 CS Instruction decode WP Write protect Control logic SCK STORE/RECALL STORE SRAM ARRAY HSB Control HOLD RECALL 128K X 8 Instruction D0-D7 register A0-A16 Address Decoder SI Data I/O register SO Status register Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 001-50091 Rev. *D Revised January 04, 2010CY14B101Q1 CY14B101Q2 CY14B101Q3 Contents Features ...............................................................................1 Write Disable (WRDI) Instruction ................................10 Block Protection ..........................................................10 Functional Overview ..........................................................1 Write Protect (WP) Pin ................................................11 Configuration ......................................................................1 Memory Access ................................................................11 Logic Block Diagram ..........................................................1 Read Sequence (READ) .............................................11 Contents ..............................................................................2 Write Sequence (WRITE) ............................................11 Pinouts ................................................................................3 Software STORE .........................................................12 Device Operation ................................................................4 Software RECALL .......................................................13 SRAM Write ...................................................................4 AutoStore Disable (ASDISB) .......................................13 SRAM Read ..................................................................4 AutoStore Enable (ASENB) .........................................13 STORE Operation .........................................................4 HOLD Pin Operation ...................................................13 AutoStore Operation ......................................................5 Maximum Ratings .............................................................14 Software Store Operation ..............................................5 DC Electrical Characteristics ..........................................14 Hardware STORE and HSB pin Operation ...................5 Data Retention and Endurance .......................................15 RECALL Operation ........................................................5 Capacitance ......................................................................15 Hardware Recall (Power Up) .........................................5 Software RECALL .........................................................5 Thermal Resistance ..........................................................15 Disabling and Enabling AutoStore .................................6 AC Test Conditions ..........................................................15 Serial Peripheral Interface .................................................6 AC Switching Characteristics .........................................16 SPI Overview .................................................................6 AutoStore or Power Up RECALL ....................................17 SPI Modes .....................................................................7 Software Controlled STORE and RECALL Cycles ........18 SPI Operating Features ......................................................8 Hardware STORE Cycle ...................................................19 Power Up .......................................................................8 Part Numbering Nomenclature ........................................20 Power On Reset ............................................................8 Ordering Information ........................................................20 Power Down ..................................................................8 Active Power and Standby Power Modes .....................8 Package Diagrams ............................................................21 SPI Functional Description ................................................8 Document History Page ..................................................23 Status Register ...................................................................9 Sales, Solutions, and Legal Information ........................24 Read Status Register (RDSR) Instruction .....................9 Worldwide Sales and Design Support .........................24 Write Status Register (WRSR) Instruction ....................9 Products ......................................................................24 PSoC Solutions ..........................................................24 Write Protection and Block Protection ...........................10 Write Enable (WREN) Instruction ................................10 Document : 001-50091 Rev. *D Page 2 of 24