CY14B108K CY14B108M 8-Mbit (1024 K 8/512 K 16) nvSRAM with Real Time Clock 8-Mbit (1024 K 8/512 K 16) nvSRAM with Real Time Clock Watchdog timer Features Clock alarm with programmable interrupts 25 ns and 45 ns access times Capacitor or battery backup for RTC Internally organized as 1024 K 8 (CY14B108K) or 512 K 16 (CY14B108M) Industrial temperature Hands off automatic STORE on power-down with only a small 44 and 54-pin thin small outline package (TSOP) Type II capacitor Pb-free and restriction of hazardous substances (RoHS) STORE to QuantumTrap nonvolatile elements is initiated by compliant software, device pin, or AutoStore on power-down Functional Description RECALL to SRAM initiated by software or power-up The Cypress CY14B108K/CY14B108M combines a 8-Mbit High reliability nonvolatile static RAM (nvSRAM) with a full featured RTC in a Infinite Read, Write, and RECALL cycles monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the 1 million STORE cycles to QuantumTrap worlds most reliable nonvolatile memory. The SRAM is read and 20 year data retention written infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. Single 3 V +20%, 10% operation The RTC function provides an accurate clock with leap year Data integrity of Cypress nonvolatile static RAM (nvSRAM) tracking and a programmable, high accuracy oscillator. The combined with full-featured real time clock (RTC) alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control. For a complete list of related documentation, click here. Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 33. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-47378 Rev. *N Revised November 23, 2017CY14B108K CY14B108M 1, 2, 3 Logic Block Diagram V V Quatrum CAP CC Trap 2048 X 2048 X 2 V A POWER RTCbat 0 R CONTROL A STORE 1 V O RTCcap A 2 W RECALL A 3 STORE/RECALL A D 4 HSB CONTROL E STATIC RAM A 5 C ARRAY A 6 O 2048 X 2048 X 2 A 7 D SOFTWARE A A - A 8 14 2 DETECT E A 17 R A 18 A 19 DQ 0 DQ 1 DQ 2 X out DQ 3 RTC X in DQ I 4 INT N DQ 5 P DQ U 6 T DQ 7 B COLUMN I/O U MUX A - A 19 0 DQ 8 F DQ F 9 E OE DQ 10 R COLUMN DEC WE DQ S 11 DQ 12 DQ 13 CE DQ 14 BLE A A A A A A A A 9 10 11 12 13 14 15 16 DQ 15 BHE Notes 1. Address A A for 8 configuration and Address A A for 16 configuration. 0 19 0 18 2. Data DQ DQ for 8 configuration and Data DQ DQ for 16 configuration. 0 7 0 15 3. BHE and BLE are applicable for 16 configuration only. Document Number: 001-47378 Rev. *N Page 2 of 36