CY14B256KA 256-Kbit (32 K 8) nvSRAM with Real Time Clock 256-Kbit (32 K 8) nvSRAM with Real Time Clock Industry standard configurations Features Single 3 V +20%, 10% operation 256-Kbit nonvolatile static random access memory (nvSRAM) Industrial temperature 25 ns and 45 ns access times 48-pin shrink small-outline package (SSOP) Internally organized as 32 K 8 (CY14B256KA) Pb-free and Restriction of hazardous substances (RoHS) Hands off automatic STORE on power-down with only a small compliant capacitor Functional Description STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power-down The Cypress CY14B256KA combines a 256-Kbit nonvolatile RECALL to SRAM initiated on power-up or by software static RAM with a full featured real time clock in a monolithic High reliability integrated circuit. The embedded nonvolatile elements Infinite Read, Write, and RECALL cycles incorporate QuantumTrap technology producing the worlds 1 million STORE cycles to QuantumTrap most reliable nonvolatile memory. The SRAM is read and written 20 year data retention an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. Real time clock (RTC) The real time clock function provides an accurate clock with leap Full-featured real time clock year tracking and a programmable, high accuracy oscillator. The Watchdog timer alarm function is programmable for periodic minutes, hours, Clock alarm with programmable interrupts days, or months alarms. There is also a programmable watchdog Capacitor or battery backup for RTC timer for process control. Backup current of 0.35 A (Typ) For a complete list of related documentation, click here. Logic Block Diagram Logic Block Diagram V V CC CAP QuantumTrap 512 X 512 V RTCbat POWER A 5 STORE CONTROL V RTCcap A 6 A 7 RECALL STORE/ A STATIC RAM 8 RECALL HSB ARRAY A 9 CONTROL A 512 X 512 11 A 12 A 13 SOFTWARE A 14 A - A 14 DETECT 0 DQ COLUMN IO 0 DQ 1 COLUMN DEC DQ 2 x out DQ x 3 RTC in INT DQ 4 DQ A A A A A A 5 0 1 2 3 4 10 DQ 6 DQ 7 A - A MUX 14 0 OE CE WE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-55720 Rev. *I Revised November 14, 2014 INPUT BUFFERS ROW DECODERCY14B256KA Contents Pinouts ..............................................................................3 DC Electrical Characteristics ........................................ 16 Pin Definitions ..................................................................3 Data Retention and Endurance ..................................... 17 Device Operation ..............................................................4 Capacitance ....................................................................17 SRAM Read ................................................................4 Thermal Resistance ........................................................ 17 SRAM Write .................................................................4 AC Test Loads ................................................................ 18 AutoStore Operation ....................................................4 AC Test Conditions ........................................................ 18 Hardware STORE (HSB) Operation ............................4 RTC Characteristics ....................................................... 18 Hardware RECALL (Power-Up) ..................................5 AC Switching Characteristics ....................................... 19 Software STORE .........................................................5 SRAM Read Cycle .................................................... 19 Software RECALL .......................................................5 SRAM Write Cycle ..................................................... 19 Preventing AutoStore ..................................................6 AutoStore/Power-Up RECALL ....................................... 21 Data Protection ............................................................6 Switching Waveforms .................................................... 21 Real Time Clock Operation ..............................................7 Software Controlled STORE/RECALL Cycle ................ 22 nvTIME Operation .......................................................7 Switching Waveforms .................................................... 22 Clock Operations .........................................................7 Hardware STORE Cycle ................................................. 23 Reading the Clock .......................................................7 Switching Waveforms .................................................... 23 Setting the Clock .........................................................7 Truth Table For SRAM Operations ................................ 24 Backup Power .............................................................7 Ordering Information ...................................................... 24 Stopping and Starting the Oscillator ............................7 Ordering Code Definitions ......................................... 24 Calibrating the Clock ...................................................8 Package Diagram ............................................................ 25 Alarm ...........................................................................8 Acronyms ........................................................................26 Watchdog Timer ..........................................................8 Document Conventions ................................................. 26 Power Monitor .............................................................9 Units of Measure ....................................................... 26 Interrupts .....................................................................9 Document History Page ................................................. 27 Interrupt Register .........................................................9 Sales, Solutions, and Legal Information ...................... 28 Flags Register .............................................................9 Worldwide Sales and Design Support ....................... 28 RTC External Components .......................................10 Products ....................................................................28 PCB Design Considerations for RTC ............................11 PSoC Solutions ...................................................... 28 Layout requirements ..................................................11 Cypress Developer Community ................................. 28 Maximum Ratings ...........................................................16 Technical Support ..................................................... 28 Operating Range .............................................................16 Document Number: 001-55720 Rev. *I Page 2 of 28