Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14C512PA CY14B512PA CY14E512PA 512-Kbit (64 K 8) SPI nvSRAM with Real Time Clock 512-Kbit (64 K 8) SPI nvSRAM with Real Time Clock Write protection Features Hardware protection using Write Protect (WP) pin 512-Kbit nonvolatile static random access memory (nvSRAM) Software protection using Write Disable instruction Internally organized as 64 K 8 Software block protection for 1/4, 1/2, or entire array STORE to QuantumTrap nonvolatile elements initiated Low power consumption automatically on power-down (AutoStore) or by using SPI Average active current of 3 mA at 40 MHz operation instruction (Software STORE) or HSB pin (Hardware Average standby mode current of 250 A STORE) RECALL to SRAM initiated on power-up (Power-Up Sleep mode current of 8 A RECALL) or by SPI instruction (Software RECALL) Industry standard configurations Automatic STORE on power-down with a small capacitor Operating voltages: High reliability CY14C512PA: V = 2.4 V to 2.6 V CC Infinite read, write, and RECALL cycles CY14B512PA: V = 2.7 V to 3.6 V CC 1 million STORE cycles to QuantumTrap CY14E512PA: V = 4.5 V to 5.5 V CC Data retention: 20 years at 85 C Industrial temperature 16-pin small outline integrated circuit (SOIC) package Real time clock (RTC) Restriction of hazardous substances (RoHS) compliant Full-featured RTC Watchdog timer Overview Clock alarm with programmable interrupts 1 Backup power fail indication The Cypress CY14X512PA combines a 512-Kbit nvSRAM with Square wave output with programmable frequency (1 Hz, a full-featured RTC in a monolithic integrated circuit with serial 512 Hz, 4096 Hz, 32.768 kHz) SPI interface. The memory is organized as 64 K words of 8 bits Capacitor or battery backup for RTC each. The embedded nonvolatile elements incorporate the Backup current of 0.45 A (typical) QuantumTrap technology, creating the worlds most reliable nonvolatile memory. The SRAM provides infinite read and write 40 MHz, and 104 MHz High-speed serial peripheral interface (SPI) cycles, while the QuantumTrap cells provide highly reliable 40 MHz clock rate SPI write and read with zero cycle delay nonvolatile storage of data. Data transfers from SRAM to the 104 MHz clock rate SPI write and read (with special fast read nonvolatile elements (STORE operation) takes place instructions) automatically at power-down. On power-up, data is restored to Supports SPI mode 0 (0,0) and mode 3 (1,1) the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations SPI access to special functions through SPI instruction. Nonvolatile STORE/RECALL 8-byte serial number For a complete list of related documentation, click here. Manufacturer ID and Product ID Sleep mode V V V V CC CAP RTCcap RTCbat Logic Block Diagram Serial Number 8 x 8 Power Control Manufacturer ID / Block Product ID QuantumTrap 64 K x 8 SLEEP STORE SRAM RDSN/WRSN/RDID SI Memory 64 K x 8 RECALL READ/WRITE Data & CS SPI Control Logic Address STORE/RECALL/ASENB/ASDISB SCK Write Protection Control Instruction decoder WP SO RDRTC/WRTC WRSR/RDSR/WREN Status Register X in RTC Control Logic Registers INT/SQW Counters X out Note 1. This device will be referred to as nvSRAM throughout the document. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-65268 Rev. *I Revised January 16, 2018