CY14V101PS 1-Mbit (128K 8) Quad SPI nvSRAM with Real Time Clock Temperature range Features Industrial: 40 C to 85 C Density Packages 1 Mbit (128K 8) 16-pin SOIC Bandwidth 108-MHz high-speed interface Functional Overview Read and write at 54 MBps The Cypress CY14V101PS combines a 1-Mbit nvSRAM with a Serial Peripheral Interface QPI interface. The QPI allows writing and reading the memory in Clock polarity and phase modes 0 and 3 either a single (one I/O channel for one bit per clock cycle), dual Multi I/O option Single SPI (SPI), Dual SPI (DPI), and Quad (two I/O channels for two bits per clock cycle), or quad (four I/O SPI (QPI) channels for four bits per clock cycle) through the use of selected High reliability opcodes. Infinite read, write, and RECALL cycles The memory is organized as 128 Kbytes each consisting of One million STORE cycles to nonvolatile elements (SONOS SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The FLASH Quantum trap) SRAM provides infinite read and write cycles, while the Data retention: 20 years at 85 C nonvolatile cells provide highly reliable storage of data. Data transfers from SRAM to the nonvolatile cells (STORE operation) Read take place automatically at power-down. On power-up, data is Commands: Standard, Fast, Dual I/O, and Quad I/O restored to the SRAM from the nonvolatile cells (RECALL Modes: Burst Wrap, Continuous (XIP) operation). The user can initiate the STORE and RECALL operations through SPI instructions. Write Commands: Standard, Fast, Dual I/O, and Quad I/O Modes: Burst Wrap Data protection Hardware: Through Write Protect Pin (WP) Software: Through Write Disable instruction Block Protection: Status Register bits to control protection Special instructions STORE/RECALL: Transfer data between SRAM and Quantum Trap nvSRAM Serial Number: 8-byte customer selectable (OTP) Identification Number: 4-byte Manufacturer ID and Product ID Store from SRAM to nonvolatile SONOS FLASH Quantum Trap AutoStore: Initiated automatically at power-down with a small capacitor (V ) CAP Software: Using SPI instruction (STORE) Hardware: HSB pin Recall from nonvolatile SONOS FLASH Quantum Trap to SRAM Auto RECALL: Initiated automatically at power-up Software: Using SPI instruction (RECALL) Low-power modes Sleep: Average current = 380 A at 85 C Hibernate: Average current = 8 A at 85 C Operating supply voltages Core V : 2.7 V to 3.6 V CC I/O V : 1.71 V to 2.0 V CCQ Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-94176 Rev. *J Revised November 24, 2017CY14V101PS Logic Block Diagram Serial Number Status Configuration Manufacturer ID Registers Product ID Nonvolatile Array (128K x 8) NC (I/O3) HSB STORE SPI/DPI/QPI SI (I/O0) Control Logic Memory Control SRAM RECALL CS Array Write Protection Address & Data (128K x 8) SCK Instruction Decoder WP (I/O2) SO (I/O1) SLEEP/HIBERNATE V CC Power Control V CCQ Block V SS V CAP V RTCBAT XIN RTC Logic INT/SQW Registers / Counters X OUT Document Number: 001-94176 Rev. *J Page 2 of 67