Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14V104LA CY14V104NA 4-Mbit (512 K 8 / 256 K 16) nvSRAM 4-Mbit (512 K 8 / 256 K 16) nvSRAM Features Functional Description 25 ns and 45 ns access times The Cypress CY14V104LA/CY14V104NA is a fast static RAM, with a non-volatile element in each memory cell. The memory is Internally organized as 512 K 8 (CY14V104LA) or 256 K 16 organized as 512 K bytes of 8 bits each or 256 K words of 16 bits (CY14V104NA) each. The embedded non-volatile elements incorporate QuantumTrap technology, producing the worlds most reliable Hands off automatic STORE on power-down with only a small non-volatile memory. The SRAM provides infinite read and write capacitor cycles, while independent non-volatile data resides in the highly STORE to QuantumTrap non-volatile elements initiated by reliable QuantumTrap cell. Data transfers from the SRAM to the software, device pin, or AutoStore on power-down non-volatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to RECALL to SRAM initiated by software or power-up the SRAM (the RECALL operation) from the non-volatile Infinite read, write, and recall cycles memory. Both the STORE and RECALL operations are also available under software control. 1-million STORE cycles to QuantumTrap For a complete list of related documentation, click here. 20 year data retention Core V = 3.0 V to 3.6 V IO V = 1.65 V to 1.95 V CC CCQ Industrial temperature 48-ball fine-pitch ball grid array (FBGA) package Pb-free and restriction of hazardous substances (RoHS) compliance 1, 2, 3 Logic Block Diagram V V V CC CCQ CAP Quatrum Trap 2048 X 2048 A POWER 0 R CONTROL A STORE 1 O A 2 W RECALL A 3 STORE/RECALL A D 4 HSB CONTROL A E STATIC RAM 5 A C ARRAY 6 O 2048 X 2048 A 7 SOFTWARE D A A - A 8 14 2 DETECT A E 17 R A 18 DQ 0 DQ 1 DQ 2 DQ 3 I DQ 4 N DQ 5 P U DQ 6 T DQ 7 B COLUMN I/O U DQ 8 F DQ F 9 E OE DQ 10 COLUMN DEC R WE DQ 11 S DQ 12 DQ 13 CE DQ 14 BLE A A A A A A A A 9 10 11 12 13 14 15 16 DQ 15 BHE Notes 1. Address A A for 8 configuration and Address A A for 16 configuration. 0 18 0 17 2. Data DQ DQ for 8 configuration and Data DQ DQ for 16 configuration. 0 7 0 15 3. BHE and BLE are applicable for 16 configuration only. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-53954 Rev. *H Revised November 5, 2014