CY62126EV18LL-70BVXI Infineon

CY62126EV18 MoBL 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM Features Functional Description High speed: 70 ns The CY62126EV18 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features Temperature ranges advanced circuit design to provide ultra low active current. This Industrial: 40 C to +85 C is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an Voltage range: 1.65 V to 1.95 V automatic power down feature that significantly reduces power Pin compatible with CY62126EV30 consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more Ultra low standby power than 99 percent when deselected (CE HIGH). The input and Typical standby current: 1 A output pins (I/O through I/O ) are placed in a high-impedance 0 15 Maximum standby current: 4 A state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Ultra low active power Enable are disabled (BHE, BLE HIGH) or during a write Typical active current: 1.3 mA at f = 1 MHz operation (CE LOW and WE LOW). Easy memory expansion with CE and OE features To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data Automatic power down when deselected from I/O pins (I/O through I/O ) is written into the location 0 7 Complementary metal oxide semiconductor (CMOS) for specified on the address pins (A through A ). If Byte High 0 15 optimum speed and power Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I/O ) is written into the location specified on the address pins 15 Offered in Pb-free 48-ball very fine-pitch ball grid array (A through A ). 0 15 (VFBGA) package To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 64K x 16 6 A 5 I/O I/O RAM Array 0 7 A 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-94739 Rev. *B Revised January 4, 2018 ROW DECODER A 11 A 12 A 13 A 14 A 15 SENSE AMPS CY62126EV18 MoBL Contents Pin Configuration ............................................................. 3 Ordering Information...................................................... 12 Product Portfolio .............................................................. 3 Ordering Code Definitions......................................... 12 Maximum Ratings............................................................. 4 Package Diagrams.......................................................... 13 Operating Range............................................................... 4 Acronyms........................................................................ 14 Electrical Characteristics................................................. 4 Document Conventions ................................................. 14 Capacitance ...................................................................... 4 Units of Measure ....................................................... 14 Thermal Resistance.......................................................... 5 Document History Page................................................. 15 AC Test Loads and Waveforms....................................... 5 Sales, Solutions, and Legal Information ...................... 16 Data Retention Characteristics ....................................... 6 Worldwide Sales and Design Support....................... 16 Data Retention Waveform................................................ 6 Switching Characteristics................................................ 7 Switching Waveforms ...................................................... 8 Truth Table...................................................................... 11 Document Number: 001-94739 Rev. *B Page 2 of 16