Precision Edge 3.3V, 3.2Gbps DUAL, DIFFERENTIAL Micrel, Inc. SY89543L Precision Edge 2:1 LVDS MULTIPLEXER with SY89543L INTERNAL TERMINATION FEATURES Dual 2:1 multiplexer Precision Edge Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput DESCRIPTION < 510ps In-to-Out t pd The SY89543L includes two precision, high-speed 2:1 < 150ps t /t r f differential Muxes with LVDS (350mV) compatible outputs Ultra-low jitter design: with a guaranteed data rate throughput of 3.2Gbps over < 1ps random jitter RMS temperature and voltage. < 10ps deterministic jitter PP The SY89543L differential inputs include a unique, 3-pin < 10ps total jitter (clock) internal termination that allows access to the termination PP network through a V pin. This feature allows the device to < 0.7ps crosstalk-induced jitter T RMS easily interface to different logic standards, both AC- and Unique input isolation design minimizes crosstalk DC-coupled without external resistor-bias and termination Internal input termination networks. The result is a clean, stub-free, low jitter interface Unique input termination and V pin accepts DC- solution. T coupled and AC-coupled inputs (LVDS, LVPECL, The SY89543L operates from a single 3.3V supply, and CML) is guaranteed over the full industrial temperature range 350mV LVDS output swing (40C to +85C). For applications that require a 2.5V supply, consider the SY89542U. The SY89543L is part of a Micrels CMOS/TTL compatible MUX select Precision Edge product family. All support documentation Power supply 3.3V +10% can be found on Micrels web site at www.micrel.com. 40 to +85C temperature range Available in 32-pin (5mm x 5mm) MLF package APPLICATIONS Redundant clock/data switchover SONET/SDH multi-channel select applications Fiber Channel applications GigE applications FUNCTIONAL BLOCK DIAGRAM INA0 INB0 50 50 V V TA0 TB0 50 50 2:1 MUX 2:1 MUX /INA0 /INB0 0 0 LVDS LVDS QA QB MUX A MUX B /QA /QB 1 1 S S INA1 INB1 50 50 V V TA1 TB1 50 50 /INA1 /INB1 SELA (CMOS/TTL) SELB (CMOS/TTL) Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: E Amendment: /0 M9999-041608 1 Issue Date: April 2008 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89543L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish VCC 1 24 VCC SY89543LMI MLF-32 Industrial SY89543L Sn-Pb 23 /INA0 2 INB1 VTA0 3 22 VTB 1 (2) SY89543LMITR MLF-32 Industrial SY89543L Sn-Pb 4 21 INA0 /INB1 (3) 5 20 SY89543LMG MLF-32 Industrial SY89543L with Pb-Free VCC VCC 6 19 SELA SELB Pb-Free bar-line indicator NiPdAu GND 7 18 GND (2, 3) SY89543LMGTR MLF-32 Industrial SY89543L with Pb-Free VCC 8 17 VCC 910 11 1213 14 1516 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF 3. Recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 4, 2, 32, 30, INA0, /INA0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 27, 25, 23, 21 INA1, /INA1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally INB0, /INB0, terminates to a V pin through 50 . Note that these inputs will default to an indeterminate T INB1, /INB1 state if left open. Unused differential input pairs can be terminated by connecting one input to V and the complementary input to GND through a 1k resistor. The V pin is to be CC T left open in this configuration. Please refer to the Input Interface Applications section for more details. 3, 31, 26, 22 VTA0 , VTA1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a V T VTB0, VTB1 pin. The V , V , V , V pins provide a center-tap to a termination network for TA0 TA1 TB0 TB1 maximum interface flexibility. See Input Interface Applications section for more details. 6, 19 SELA, SELB These single-ended TTL/CMOS compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. 1, 5, 8, 17, 20, VCC Positive Power Supply: Bypass with 0.1 F 0.01 F low ESR capacitors. The 0.01 F 24, 28, 29 capacitor should be as close to V pin as possible. CC 10, 11, 14, 15 QA, /QA, Differential Outputs: This differential LVDS output pair provides a copy of the selected QB, /QB input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the Truth Table for details. Unused output pairs must be terminated with 100 across the differential pair. 7, 9, 12, 13, 16, 18 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed pad M9999-041608 2 hbwhelp micrel.com or (408) 955-1690 INA1 GND QA VTA1 /QA /INA1 GND VCC GND VCC QB INB0 /QB VTB0 /INB0 GND