74HC73D-Q100J Nexperia

74HC73-Q100 Dual JK flip-flop with reset negative-edge trigger Rev. 1 4 December 2020 Product data sheet 1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C CMOS low-power dissipation Wide supply voltage range from 2.0 to 6.0 V High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC73D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mmNexperia 74HC73-Q100 Dual JK flip-flop with reset negative-edge trigger 4. Functional diagram 14 1J 1Q 12 J Q FF1 1 1CP CP 3 1K 1Q 13 K Q R 2 1R 14 1J 12 1 C1 3 7 2J 2Q 9 14 1J 1Q 12 1K J Q J Q 13 7 2J 2Q 9 2 R FF2 FF 1 1CP 5 2CP CP CP 5 2CP 7 1J 3 1K 1Q 13 9 10 2K 2Q 8 K Q 5 K Q 10 2K 2Q 8 C1 10 R R 1K 8 6 6 2R R 1R 2R 2 6 001aab981 001aab979 001aab980 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol C C C C K Q J C C C C R Q C CP 001aab982 C Fig. 4. Logic diagram (one flip-flop) 74HC73 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 1 4 December 2020 2 / 12