74LVTH16374ADGG,18 Nexperia

74LVT16374A 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop 3-state Rev. 12 6 August 2021 Product data sheet 1. General description The 74LVT16374A 74LVTH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. 2. Features and benefits 16-bit edge-triggered flip-flop 3-state buffers Output capability: +64 mA and -32 mA Wide supply voltage range from 2.7 to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs. (74LVTH16374A only) Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT16374ADGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package 48 leads SOT362-1 body width 6.1 mm 74LVTH16374ADGGNexperia 74LVT16374A 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop 3-state 4. Functional diagram 47 46 44 43 41 40 38 37 1 EN1 1OE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1CP C3 24 2OE EN2 25 48 1CP 2CP C4 47 2 1 1OE 1D0 3D 1 1Q0 46 3 1D1 1Q1 44 5 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1D2 1Q2 43 6 1D3 1Q3 41 8 2 3 5 6 8 9 11 12 1D4 1Q4 40 9 1D5 1Q5 36 35 33 32 30 29 27 26 38 11 1D6 1Q6 37 12 1D7 1Q7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 36 13 2D0 4D 2 2Q0 35 14 2D1 2Q1 25 2CP 33 16 2D2 2Q2 32 17 2D3 2Q3 24 2OE 30 19 2D4 2Q4 29 20 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D5 2Q5 27 22 2D6 2Q6 26 23 13 14 16 17 19 20 22 23 2D7 2Q7 001aac369 001aaa254 Fig. 1. Logic symbol Fig. 2. IEC logic symbol nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 001aac371 Fig. 3. Logic diagram 74LVT LVTH16374A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 12 6 August 2021 2 / 13