74LVC74APW-Q100J NXP

74LVC74A-Q100 Dual D-type flip-flop with set and reset positive-edge trigger Rev. 2 5 April 2013 Product data sheet 1. General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC74AD-Q100 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC74APW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC74ABQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram 1SD 4 SD 1Q 1D 2 D Q 5 1CP 3 CP FF 1Q Q 6 RD 4 410 S 5 1RD 3 1 1SD 2SD C1 2 2SD 1D 6 10 SD 1 1Q 5 2 1D R D Q 12 2D 2Q 9 SD 2Q 2D 3 1CP 12 9 D Q CP 10 11 2CP FF S 9 2CP 1Q 6 11 CP 11 Q C1 8 FF 2Q 2Q 12 RD Q 8 1D 8 13 RD 1RD 2RD R 2RD 113 mna420 mna418 mna419 13 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram 74LVC74A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 5 April 2013 2 of 18