PH9230CL,115 NXP

PH955L N-channel TrenchMOS logic level FET Rev. 02 19 February 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low Suitable for logic level gate drive on-state resistance sources 1.3 Applications DC-to-DC convertors Motors, lamps and solenoids General purpose power switching Portable equipment 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C T 150 C - - 55 V DS j j I drain current T =25C V =5V - - 62.5 A D mb GS see Figure 1 see Figure 3 P total power T = 25 C see Figure 2 - - 62.5 W tot mb dissipation Dynamic characteristics Q gate-drain charge V =5V I =25A - 16.4 - nC GD GS D V =44V T =25C DS j see Figure 11 see Figure 12 Static characteristics R drain-source V =10V I =25A -6.2 8.3 m DSon GS D on-state resistance T = 25 C see Figure 10 jNexperia PH955L N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1S source mb D 2S source 3S source G 4G gate mbb076 S mb D mounting base connected to 1234 drain SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PH955L LFPAK plastic single-ended surface-mounted package (LFPAK) 4 leads SOT669 PH955L 2 Product data sheet Rev. 02 19 February 2009 2 of 13 Nexperia B.V. 2017. All rights reserved