PHD96NQ03LT,118 NXP

PHD96NQ03LT N-channel TrenchMOS logic level FET Rev. 06 15 March 2010 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low Simple gate drive required due to low on-state resistance gate charge 1.3 Applications DC-to-DC convertors 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C T 175 C - - 25 V DS j j I drain current T =25C V =5V --75 A D mb GS see Figure 1 and 3 P total power T = 25 C see Figure 2 --115 W tot mb dissipation Dynamic characteristics Q gate-drain charge V =5V I =50A -8.4 -nC GD GS D V =15V T =25C DS j see Figure 11 Static characteristics R drain-source V =10V I =25A - 4.2 4.95 m DSon GS D on-state resistance T = 25 C see Figure 9 j V =5V I =25A -5.6 7.5 m GS D T =25C j see Figure 9 and 10PHD96NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1G gate mb D 1 2D drain 3S source G mb D mounting base connected to drain mbb076 S 2 1 3 SOT428 (DPAK) 1 It is not possible to make connection to pin 2. 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PHD96NQ03LT DPAK plastic single-ended surface-mounted package (DPAK) 3 leads (one SOT428 lead cropped) PHD96NQ03LT 6 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 15 March 2010 2 of 13