PMN49EN,135 NXP

PMN49EN N-channel TrenchMOS logic level FET Rev. 01 13 April 2007 Product data sheet 1. Product prole 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features n Logic level threshold n Fast switching 1.3 Applications n Battery management n High-speed switching 1.4 Quick reference data n V 30 V n I 4.6 A DS D n R 47 m n Q = 1.6 nC (typ) DSon GD 2. Pinning information Table 1. Pinning Pin Description Simplied outline Symbol 1, 2, 5, 6 drain (D) 6 5 4 D 3 gate (G) 4 source (S) G 132 mbb076 S SOT457 (TSOP6)PMN49EN NXP Semiconductors N-channel TrenchMOS logic level FET 3. Ordering information Table 2. Ordering information Type number Package Name Description Version PMN49EN SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage 25 C T 150 C - 30 V DS j V drain-gate voltage (DC) 25 C T 150 C; R =20k -30 V DGR j GS V gate-source voltage - 20 V GS I drain current T =25 C; V = 10 V; see Figure 2 and 3 - 4.6 A D sp GS T = 100 C; V = 10 V; see Figure 2 - 2.9 A sp GS I peak drain current T =25 C; pulsed; t 10 s; see Figure 3 - 18.4 A DM sp p P total power dissipation T =25 C; see Figure 1 - 1.75 W tot sp T storage temperature - 55 +150 C stg T junction temperature - 55 +150 C j Source-drain diode I source current T =25 C - 1.4 A S sp I peak source current T =25 C; pulsed; t 10 s - 5.6 A SM sp p PMN49EN_1 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 13 April 2007 2 of 12