ESD7124MUTBG ON Semiconductor

ESD7124 4-Channel Low Capacitance Dual-Voltage ESD and Surge Protection Array Features ESD7124 PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 4Channel, 6Lead, UDFN8 Package Top View Bottom View (Pins Down View) (Pins Up View) Pin Name Type Description 12 3 4 6 5 1 V HV V HV ESD Channel CC DD 2 CH1 I/O LV Lowcapacitance ESD Channel XX M 3 CH2 I/O LV Lowcapacitance ESD Channel Pin 1 Marking 4 CH3 I/O LV Lowcapacitance ESD Channel 5 GND Ground 65 1 2 3 4 6 GND Ground 6Lead UDFN SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Temperature Range 55 to +125 C Storage Temperature Range 65 to +150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. ELECTRICAL CHARACTERISTICS Reverse Working Breakdown Reverse Current Junction Capactance Voltage Voltage Vbr (V) Cj(pF) Leakage Ir ( A) Rdyn Vrwm (V) at 1 mA at Vrwm Vr = 0 V, f = 1 MHz Max Min Typ Max Typ Typ Max Device Name Pin2-4 (LV) 3.3 5.5 6.5 1 1 0.35 0.5 Pin1 (HV) 12 13.3 14 1 Clamping Voltage Vc (V) Max Ratings tp = 8 x 20 s tp = 8 x 20 s Ipp = 1 A Ipp = 16 A Ipp (A) Vc Max Ipp (V) Typ Typ Max Max Device Name Pin1 (HV) 15 16 100 27 Pin2-4 (LV) 9.5 Parameter Symbol Conditions Min Typ Max Unit Clamping Voltage V 16.8 V IEC 6100042 Level 2 equivalent C I = 8 A TLP (Note 1) PP (4 kV Contact, 4 kV Air) All Devices Pin2-4(LV) 24.9 See Figures 3 6 IEC 6100042 Level 4 equivalent I = 16 A PP (8 kV Contact, 15 kV Air) 1. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 50 , t = 100 ns, t = 4 ns, averaging window t = 30 ns to t = 60 ns. 0 p r 1 2