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HS source and LS Drain Max r = 5.8 m at V = 10 V, I = 15 A DS(on) GS D internally connected for half/full bridge, low source inductance Max r = 8.7 m at V = 4.5 V, I = 12 A package, low r /Qg FOM silicon. DS(on) GS D DS(on) Ideal for Flexible Layout in Primary Side of Bridge Topology Applications 100% UIL Tested Synchronous Buck : Primary Switch of Half / Full bridge Kelvin High Side MOSFET Drive Pin-out Capability Converter for Telecom Termination is Lead-free and RoHS Compliant Motor Bridge : Primary Switch of Half / Full bridge Converter for BLDC Motor MV POL : 48V Synchronous Buck Switch Pin 1 1 12 D1 G1 Pin 1 2 11 D1 G1R D2/S1 3 10 D1 D2/S1 4 9 G2 5 8 S2 D2/S1 6 7 S2 D2/S1 Power 3.3 x 5 MOSFET Maximum Ratings T = 25 C unless otherwise noted. A Symbol Parameter Ratings Units V Drain to Source Voltage 60 V DS V Gate to Source Voltage 20 V GS Drain Current -Continuous T = 25 C (Note 5) 67 C -Continuous T = 100 C (Note 5) 47 C I A D -Continuous T = 25 C (Note 1a) 15 A -Pulsed (Note 4) 304 E Single Pulse Avalanche Energy (Note 3) 181 mJ AS Power Dissipation T = 25 C 44 C P Power Dissipation T = 25 C (Note 1a) 2.5 W D A Power Dissipation T = 25 C (Note 1b) 1.1 A T , T Operating and Storage Junction Temperature Range -55 to +175 C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 3.4 JC R Thermal Resistance, Junction to Ambient (Note 1a) 60 C/W JA R Thermal Resistance, Junction to Ambient (Note 1b) 130 JA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 8260LT FDMD8260LET60 Power 3.3 x 5 13 12 mm 3000 units 1 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMD8260LET60 Rev.1.0