MM74HC573 3-STATE Octal D-Type Latch September 1983 Revised May 2005 MM74HC573 3-STATE Octal D-Type Latch General Description Features The MM74HC573 high speed octal D-type latches utilize Typical propagation delay: 18 ns advanced silicon-gate P-well CMOS technology. They pos- Wide operating voltage range: 2 to 6 volts sess the high noise immunity and low power consumption Low input current: 1 PA maximum of standard CMOS integrated circuits, as well as the ability Low quiescent current: 80 PA maximum (74HC Series) to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ide- Compatible with bus-oriented systems ally suited for interfacing with bus lines in a bus organized Output drive capability: 15 LS-TTL loads system. When the LATCH ENABLE(LE) input is HIGH, the Q out- puts will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the out- puts until LATCH ENABLE returns HIGH again. When a HIGH logic level is applied to the OUTPUT CONTROL OC input, all outputs go to a HIGH impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function and pinout com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Code: Order Number Package Number Package Description MM74HC573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Output Latch Data Output Control Enable L HHH LH L L LL X Q 0 HX X Z H HIGH Level L LOW Level Q Level of output before steady-state input conditions were established. 0 Z High Impedance X Don t Care Top View 2005 Fairchild Semiconductor Corporation DS005212 www.fairchildsemi.comAbsolute Maximum Ratings(Note 1) Recommended Operating (Note 2) Conditions Supply Voltage (V ) 0.5 to 7.0V CC Min Max Units DC Input Voltage (V ) 1.5 to V 1.5V IN CC Supply Voltage (V)26V CC DC Output Voltage (V ) 0.5 to V 0.5V OUT CC DC Input or Output Voltage 0 V V CC Clamp Diode Current (I , I ) r20 mA IK OK (V , V ) IN OUT DC Output Current, per pin (I ) r35 mA OUT Operating Temperature Range (T ) 40 85 qC A DC V or GND Current, per pin (I ) r70 mA CC CC Input Rise or Fall Times Storage Temperature Range (T ) 65qC to 150qC STG (t , t ) V 2.0V 1000 ns r f CC Power Dissipation (P ) D V 4.5V 500 ns CC (Note 3) 600 mW V 6.0V 400 ns CC S.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Lead Temperature (T ) L Note 2: Unless otherwise specified all voltages are referenced to ground. (Soldering 10 seconds) 260qC Note 3: Power Dissipation temperature derating plastic N package: 12 mW/qC from 65 qC to 85 qC. DC Electrical Characteristics (Note 4) T 25 qCT 40 to 85qCT 55 to 125qC A A A Symbol Parameter Conditions V Units CC Typ Guaranteed Limits V Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V IH Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V IL Voltage 4.5V1.351.351.35V 6.0V 1.8 1.8 1.8 V V Minimum HIGH Level Output V V or V OH IN IH IL Voltage I d 20 PA 2.0V 2.0 1.9 1.9 1.9 V OUT 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V V V or V IN IH IL I d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V OUT I d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V OUT V Maximum LOW Level Output V V or V OL IN IH IL Voltage I d 20 PA 2.0V 0 0.1 0.1 0.1 V OUT 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V V or V IN IH IL I d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V OUT I d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V OUT I Maximum Input Current V V or GND 6.0V r0.1 r1.0 r1.0 PA IN IN CC I Maximum 3-STATE Output V V or GND OZ OUT CC Leakage Current OC V 6.0V r0.5 r5.0 r10 PA IH I Maximum Quiescent Supply V V or GND CC IN CC Current I 0 PA 6.0V 8.0 80 160 PA OUT I Quiescent Supply Current V 5.5V OE 1.0 1.5 1.8 2.0 mA CC CC per Input Pin V 2.4V LE 0.6 0.8 1.0 1.1 mA IN or 0.4V (Note 4) DATA 0.4 0.5 0.6 0.7 mA Note 4: For a power supply of 5V r10% the worst-case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when OH OL designing with this supply. Worst-case V and V occur at V 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst-case leakage cur- IH IL CC IH rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used. IN CC OZ www.fairchildsemi.com 2 MM74HC573