2.5 V/3.3 V ECL DUAL Differential 2:1 Multiplexer NB100LVEP56 Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The www.onsemi.com differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both LVECL and LVCMOS input voltage levels. Multiple V pins BB 24 1 are provided. The V pin, an internally generated voltage supply, is available to QFN24 BB MN SUFFIX this device only. For singleended input operation, the unused CASE 485L differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC MARKING DIAGRAM* to 0.5 mA. When not used, V should be left open. BB 24 Features 1 N100 Maximum Input Clock Frequency > 2.5 GHz Typical VP56 Maximum Input Data Rate > 2.5 Gb/s Typical ALYW 525 ps Typical Propagation Delays Low Profile QFN Package A = Assembly Location PECL Mode Operating Range: L = Wafer Lot V = 2.375 V to 3.8 V with V = 0 V CC EE Y = Year NECL Mode Operating Range: W = Work Week = PbFree Package V = 0 V with V = 2.375 V to 3.8 V CC EE (Note: Microdot may be in either location) Separate, Common Select, and Individual Select *For additional marking information, refer to (Compatible with ECL and CMOS Input Voltage Levels) Application Note AND8002/D. Q Output Will Default LOW with Inputs Open or at V EE Multiple V Outputs BB These Devices are PbFree and are RoHS Compliant ORDERING INFORMATION Device Package Shipping QFN24 92 Units / Tube NB100LVEP56MNG (PbFree) QFN24 NB100LVEP56MNR2G 3000 / (PbFree) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: May, 2021 Rev. 12 NB100LVEP56/DNB100LVEP56 Table 1. PIN FUNCTION DESCRIPTION Pin No. Default QFN State Name I/O Description 3,9,18,19, V Positive Supply Voltage. All VCC Pins must be Externally Connected to Power CC 20 Supply to Guarantee Proper Operation. 15,24 V Negative Supply Voltage. All VEE Pins must be Externally Connected to Power EE Supply to Guarantee Proper Operation. 6,12 V , ECL Reference Voltage Output BB0 V BB1 4 D0a ECL Input Low Noninverted Differential Data a Input to MUX 0. Internal 75 k to V . EE 5 D0a ECL Input High Inverted Differential Data a Input to MUX 0. Internal 75 k to V and 37 k to EE V . CC 7 D0b ECL Input Low Noninverted Differential Data b Input to MUX 0. Internal 75 k to V . EE 8 D0b ECL Input High Inverted Differential Data b Input to MUX 0. Internal 75 k to V and 37 k to EE V . CC 10 D1a ECL Input Low Noninverted Differential Data a Input to MUX 1. Internal 75 k to V . EE 11 D1a ECL Input High Inverted Differential Data a Input to MUX 1. Internal 75 k to V and 37 k to EE V . CC 13 D1b ECL Input Low Noninverted Differential Data b Input to MUX 1. Internal 75 k to V . EE 14 D1b ECL Input High Inverted Differential Data b Input to MUX 1. Internal 75 k to V and 37 k to EE V . CC 2 Q0 ECL Output Noninverted Differential Output MUX 0. Typically Terminated with 50 to V = TT V 2.0 V. CC 1 Q0 ECL Output Inverted Differential Output MUX 0. Typically Terminated with 50 to V = TT V 2.0 V. CC 17 Q1 ECL Output Noninverted Differential Output MUX 1. Typically Terminated with 50 to V = TT V 2.0 V. CC 16 Q1 ECL Output Inverted Differential Output MUX 1. Typically Terminated with 50 to V = TT V 2.0 V. CC 23 SEL0 ECL, CMOS Low Noninverted Differential Select Input to MUX 0. Internal 75 k to V . EE Input 22 COM SEL ECL, CMOS Low Noninverted Differential Common Select Input to Both MUX. Internal 75 k to Input V . EE 21 SEL1 ECL, CMOS Low Noninverted Differential Select Input to MUX 1. Internal 75 k to V . EE Input EP Exposed Pad. The exposed pad (EP) on the package bottom must be attached to a heatsinking conduit. The exposed pad may only be electrically connected to V . EE www.onsemi.com 2