NCV898032 2 MHz Automotive Grade Non-Synchronous Boost Controller The NCV898032 is an adjustable output nonsynchronous boost controller which drives an external Nchannel MOSFET. The device www.onsemi.com uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate MARKING driver. DIAGRAM Protection features include internallyset softstart, undervoltage 8 lockout, cyclebycycle current limiting and thermal shutdown. SOIC8 8980xx Additional features include low quiescent current sleep mode and D SUFFIX ALYW 8 microprocessor compatible input pin. CASE 751 1 1 Features Peak Current Mode Control with Internal Slope Compensation 8980xx = Specific Device Code 0.2 V 3% Reference Voltage for Constant Current Loads xx = 32 A = Assembly Location 2 MHz Fixed Frequency Operation L = Wafer Lot Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump Y = Year W = Work Week Input Undervoltage Lockout (UVLO) = PbFree Package Internal SoftStart Low Quiescent Current in Sleep Mode (< 10 A Typical) CyclebyCycle Current Limit Protection PIN CONNECTIONS HiccupMode Overcurrent Protection (OCP) EN 1 8 VFB Thermal Shutdown (TSD) ISNS 2 7 VC NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 GND 3 6 VIN Qualified and PPAP Capable GDRV 4 5 VDRV These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant (Top View) Typical Applications LED Lighting ORDERING INFORMATION Headlamps Device Package Shipping Backlighting NCV898032D1R2G SOIC8 2500 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2018 Rev. 2 NCV89803/DNCV898032 V g VIN 6 C g TEMP L VDRV C DRV FAULT NRVBS260T3G VDRV LOGIC 5 V o CLK EN OSC GDRV Q 1 DRIVE EN C 4 D2 o LOGIC NVTFS5C680NLWFTAG SC ISNS 2 VC CL R CSA SNS 7 GND Dn 3 + R C VFB 8 Gm C R C F1 SS V ref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin Symbol Pin No. Function 1 EN Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable timeout period. 2 ISNS Current sense input. Connect this pin to the source of the external NMOSFET, through a currentsense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance in addition to the internal. 5 VDRV Driving voltage. Internally regulated supply for driving the external N MOSFET, sourced from VIN. Bypass with a 1.0 F ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi- tion to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. www.onsemi.com 2 PWM