RFD14N05SM9A Data Sheet September 2013 N-Channel Power MOSFET Features 50V, 14A, 100 m 14A, 50V These are N-channel power MOSFETs manufactured using r = 0.100 DS(ON) the MegaFET process. This process, which uses feature Temperature Compensating PSPICE Model sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding Peak Current vs Pulse Width Curve performance. They were designed for use in applications UIS Rating Curve such as switching regulators, switching converters, motor o drivers and relay drivers. These transistors can be operated 175 C Operating Temperature directly from integrated circuits. Related Literature Formerly developmental type TA09770. - TB334 Guidelines for Soldering Surface Mount Components to PC Boards Ordering Information Symbol PART NUMBER PACKAGE BRAND D RFD14N05SM9A TO-252AA F14N05 G S Packaging JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE 2004 Fairchild Semiconductor Corporation RFD14N05SM 9A Rev. C1RFD14N05SM 9A o Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified C RFD14N05SM 9A UNITS Drain to Source Voltage (Note 1) V 50 V DSS Drain to Gate Voltage (R = 20k ) (Note 1) V 50 V GS DGR Gate to Source Voltage V 20 V GS Continuous Drain Current I 14 A D Pulsed Drain Current (Note 3) I Refer to Peak Current Curve DM Pulsed Avalanche Rating . E Refer to UIS Curve AS Power Dissipation . P 48 W D o o Derate above 25 C . 0.32 W/ C o Operating and Storage Temperature T T -55 to 175 C J, STG Maximum Temperature for Soldering o Leads at 0.063in (1.6mm) from Case for 10s T 300 C L o Package Body for 10s, See Techbrief 334 T 260 C pkg CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: o o 1. T = 25 C to 150 C. J o Electrical Specifications T = 25 C, Unless Otherwise Specified C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV I = 250 A, V = 0V (Figure 9) 50 - - V DSS D GS Gate Threshold Voltage V V = V , I = 250A2-4V GS(TH) GS DS D Zero Gate Voltage Drain Current I V = Rated BV , V = 0V - - 25 A DSS DS DSS GS o V = 0.8 x Rated BV , V = 0V, T = 150 C - - 250 A DS DSS GS C Gate to Source Leakage Current I V = 20V - - 100 nA GSS GS Drain to Source On Resistance (Note 2) r I = 14A, V = 10V, (Figure 11) - - 0.100 DS(ON) D GS Turn-On Time t V = 25V, I 14A, V = 10V, - - 60 ns ON DD D GS R = 25, R = 1.7 GS L Turn-On Delay Time t -14 - ns d(ON) (Figure 13) Rise Time t -26 - ns r Turn-Off Delay Time t -45 - ns d(OFF) Fall Time t -17 - ns f Turn-Off Time t - - 100 ns OFF Total Gate Charge Q V = 0V to 20V V = 40V, I = 14A, - - 40 nC g(TOT) GS DD D R = 2.86 L Gate Charge at 5V Q V = 0V to 10V - - 25 nC g(10) GS I = 0.4mA g(REF) Threshold Gate Charge Q V = 0V to 2V - - 1.5 nC (Figure 13) g(TH) GS Input Capacitance C V = 25V, V = 0V, f = 1MHz - 570 - pF ISS DS GS (Figure 12) Output Capacitance C - 185 - pF OSS Reverse Transfer Capacitance C -50 - pF RSS o Thermal Resistance Junction to Case R - - 3.125 C/W JC o Thermal Resistance Junction to Ambient R - - 100 C/W JA Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V I = 14A - - 1.5 V SD SD Diode Reverse Recovery Time t I = 14A, dI /dt = 100A/ s - - 125 ns rr SD SD NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). 2004 Fairchild Semiconductor Corporation RFD14N05SM 9A Rev. C1