Product Specification PE4246 Absorptive SPST UltraCMOS Product Description RF Switch: 1 - 5000 MHz The PE4246 RF Switch is designed to cover a broad range of Features applications from 1 to 5000 MHz. It is non-reflective at both Non-reflective 50-ohm RF switch RF1 and RF2 ports. This SPST switch integrates a single-pin 50-ohm (0.25 watt) terminations CMOS control interface, and provides low insertion loss while High isolation: 55 dB at 1000 MHz, operating with extremely low bias from a single +3-volt supply. 48 dB at 3000 MHz In a typical application, the high isolation PE4246 can replace multiple RF switches of lesser isolation performance. It is Low insertion loss: 0.8 dB at 1000 MHz, offered in a small 3x3 mm DFN package. 0.9 dB at 3000 MHz High linearity: +33 dBm input 1dB The PE4246 is manufactured on Peregrines UltraCMOS compression point process, a patented variation of silicon-on-insulator (SOI) CMOS/TTL single-pin control technology on a sapphire substrate, offering the performance Single +3-volt supply operation of GaAs with the economy and integration of conventional Extremely low bias: 33 A 3 V CMOS. Available in a 6-lead DFN package Figure 1. Functional Diagram Peregrine Specification 71/0008 Figure 2. Package Type 6-lead DFN RF1 RF2 ESD ESD 50 50 CMOS Control Driver CTRL Table 1. Electrical Specifications +25 C, V = 3 V (ZS = ZL = 50 ) DD Parameter Condition Minimum Typical Maximum Units 1 Operation Frequency 1 5000 MHz Operating Power CTRL=1/CTRL=0 30/24 dBm 1-2000 MHz 0.8 1.0 dB 2000-3000 MHz 0.9 1.1 dB Insertion Loss 3000-4000 MHz 1.0 1.3 dB 4000-5000 MHz 1.3 1.8 dB 1-2000 MHz 49 55 dB 2000-3000 MHz 45 48 dB Isolation 3000-4000 MHz 43 46 dB 4000-5000 MHz 40 44 dB Return Loss 1-5000 MHz 11 20 dB 3 Input 1 dB Compression 1-5000 MHz 30 33 dBm Input IP3 1-5000 MHz 50 dBm 2 Video Feedthrough 15 mV pp Switching Time 2 s Notes: 1. Device linearity will begin to degrade below 1 MHz. 2. The DC transient at the output of the switch when the control voltage is switched from Low to High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. 3. Note Absolute Maximum ratings in Table 3. Document No. 70-0090-09 www.psemi.com 2003-2010 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: PE4246 Product Specification Figure 3. Pin Configuration Device Description The PE4246 high-isolation SPST RF Switch is designed to support a variety of applications V 1 6 RF2 DD where high isolation performance is demanded and a non-reflective input and output is desired. Exposed Solder Pad GND 2 5 GND This switch is able to replace multiple lesser (bottom side) performing switches in a very small 3x3 mm DFN footprint. 3 RF1 4 CTRL Table 4. Operating Ranges Parameter Min Typ Max Unit Table 2. Pin Descriptions V Power Supply 3.0 V 2.7 3.3 DD Pin Pin Description I Power Supply Current DD No. Name 33 40 A (V = 3 V, V = 3 V) DD CNTL 1 1 V Nominal 3 V supply connection. DD T Operating temperature -40 85 C OP 3 2 GND Ground connection. Control Voltage High 0.7xV 5 V DD 2 3 RF1 RF port. Control Voltage Low 0 0.3xV V DD CMOS or TTL logic level: 4 CTRL High = RF1 to RF2 signal path Low = RF1 isolated from RF2 Table 5. Control Logic Truth Table 3 5 GND Ground connection. Control Voltage Signal Path 2 6 RF2 RF port. CTRL = CMOS or TTL High RF1 to RF2 CTRL = CMOS or TTL Low RF1 isolated from RF2 Notes: 1. A bypass capacitor should be placed as close as possible to the pin. 2. Both RF pins must be DC blocked by an external capacitor Control Logic or held at 0 V . DC 3. The exposed pad must be soldered to the ground plane for The control logic input pin (CTRL) is typically driven by proper switch performance. a 3-volt CMOS logic level signal, and has a threshold of Table 3. Absolute Maximum Ratings 50% of V . For flexibility to support systems that have DD 5-volt control logic drivers, the control logic input has Symbol Parameter/Condition Min Max Unit been designed to handle a 5-volt logic HIGH signal. (A V Power supply voltage -0.3 4.0 V minimal current will be sourced out of the V pin when DD DD the control logic input voltage level exceeds V .) DD V Voltage on CTRL input -0.3 5.5 V I T Storage temperature -65 150 C ST Electrostatic Discharge (ESD) Precautions Input power (50 ), When handling this UltraCMOS device, observe the P 33/24 dBm IN CTRL=1/CTRL=0 same precautions that you would use with other ESD- ESD voltage sensitive devices. Although this device contains V 200 V ESD (Human Body Model) circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the Exceeding absolute maximum ratings may cause rating specified in Table 3. permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute Latch-Up Avoidance maximum for extended periods may reduce reliability. Unlike conventional CMOS devices, UltraCMOS de- vices are immune to latch-up. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE4246 in the 6-lead 3x3 DFN package is MSL1. 2003-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0090-09 UltraCMOS RFIC Solutions Page 2 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: