Product Specification PE42551 SPDT UltraCMOS RF Switch Product Description 9 kHz - 6000 MHz The PE42551 RF Switch is designed to support the Features requirements of the test equipment and ATE market. This HaRP-Technology Enhanced broadband general purpose switch maintains excellent RF Eliminates Gate and Phase Lag performance and linearity from 9 kHz through 6000 MHz. The No insertion loss nor phase drift PE42551 integrates on-board CMOS control logic driven by a Fast settling time single-pin, low voltage CMOS control input. It also has a logic select pin which enables changing the logic definition of the High linearity 50 dBm IIP3 control pin. Additional features include a novel user defined Low insertion loss: 0.65 dB at 3000 MHz, logic table, enabled by the on-board CMOS circuitry. The 0.90 dB at 6000 MHz PE42551 also exhibits outstanding isolation that approaches High isolation of 29 dB at 3000 MHz, 21 dB at 6000 MHz and is offered in a small 4x4x0.85 mm 21 dB at 6000 MHz QFN package. High power 1 dB compression point of +34 dBm The PE42551 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) ESD: 500 V HBM technology on a sapphire substrate, offering the performance of Single-pin 2.75V CMOS logic control GaAs with the economy and integration of conventional CMOS. Logic select pin to change definition of logic control Reflective switch design Figure 1. Functional Diagram 20-lead 4x4x0.85 mm QFN package Peregrine Specification 71-0065 Figure 2. Package Type 20-lead 4x4x0.85 mm QFN Table 1. Electrical Specifications +25C, V = 2.75V (Z = Z = 50 ) S L DD Parameter Conditions Min Typical Max Units Operation Frequency 9 kHz 6000 MHz 9 kHz 0.55 0.65 dB Insertion Loss 3000 MHz 0.65 0.75 dB 6000 MHz 0.90 dB 3000 MHz 28 29 dB Isolation RF1 to RF2 6000 MHz 21 dB Return Loss 3000 MHz 14 18 dB RF1, RF2 and RFC 6000 MHz 14 dB Switching Time 50% CTRL to 0.1 dB final value 7 s Input 1 dB Compression 6000 MHz 32 34 dBm Input IP3 6000 MHz +50 dBm Note: Device linearity will begin to degrade below 10 MHz. Document No. 70-0350-02 www.psemi.com 2010-2012 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE42551 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V Power supply voltage -0.3 4.0 V DD Voltage on any input except V + DD V -0.3 V I for CTRL and LS inputs 0.3 V Voltage on CTRL input 4.0 V CTRL V Voltage on LS input 4.0 V LS T Storage temperature range -65 150 C ST T Operating temperature range -40 85 C OP Input Power 50 : P 9 kHz 4 MHz Fig. 4 dBm IN 4 MHz 6 GHz 31 dBm 1 V ESD voltage HBM 500 V ESD Note: 1. Human Body Model (HBM, MIL STD 883 Method 3015.7) Exceeding absolute maximum ratings may cause Table 2. Pin Descriptions permanent damage. Operation should be restricted to the limits in the Operating Ranges Pin No. Pin Name Description 1 table. Operation between operating range 13 RF2 RF2 port. maximum and absolute maximum for extended Ground Connection. Traces should be periods may reduce reliability. 1, 2, 4, 5, physically short and connected to the 6, 7, 9, 10, ground plane. This pin is connected to GND 11, 12, 14, the exposed solder pad that also must Electrostatic Discharge (ESD) Precautions 15, 19 be soldered to the ground plane for best performance. When handling this UltraCMOS device, observe the same precautions that you would use with 1 3 RF1 RF1 port. other ESD-sensitive devices. Although this device 16 CTRL CMOS level (See Table 5) contains circuitry to protect it from damage due to 1 ESD, precautions should be taken to avoid 8 RFC Common RF port for switch exceeding the rating specified. Logic Select - Used to determine the 17 LS definition for the CTRL pin (see Table 5) Moisture Sensitivity Level Negative power supply. Apply nominal 18 V SS 2 The Moisture Sensitivity Level rating for the -2.75V supply PE42551 in the 20-lead 4x4x0.85 mm QFN 20 V Nominal 2.75V supply connection DD package is MSL1. Paddle GND Exposed Ground Paddle Notes: 1. All RF pins must be held at 0 VDC or the DC must be blocked with Latch-Up Avoidance an external series capacitor 2. Use V (pin 13, V = -V ) to bypass and disable internal negative SS SS DD Unlike conventional CMOS devices, UltraCMOS voltage generator. Connect V (pin 13) to GND (V = 0V) to enable SS SS devices are immune to latch-up. internal negative voltage generator. 2010-2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0350-02 UltraCMOS RFIC Solutions Page 2 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: