Product Specification PE42552 SPDT UltraCMOS RF Switch DC - 7500 MHz Product Description Features The PE42552 RF Switch is designed for use in Test/ATE, HaRP-Technology-Enhanced cellular and other wireless applications. This broadband general Eliminates Gate and Phase Lag purpose switch maintains excellent RF performance and No insertion loss or phase drift linearity from DC through 7500 MHz. The PE42552 integrates Fast settling time on-board CMOS control logic driven by a single-pin, low voltage CMOS control input. It also has a logic select pin which enables High linearity: 65 dBm IIP3 changing the logic definition of the control pin. Additional Low insertion loss: 0.65 dB at 3.0 GHz, features include a novel user defined logic table, enabled by the 0.85 dB at 6.0 GHz, 1.0 at 7.5 GHz on-board CMOS circuitry. The PE42552 also exhibits High isolation of 47 dB at 3.0 GHz, outstanding isolation of 44 dB at 7500 MHz, fast settling time, 44 dB at 7.5 GHz and is offered in a tiny 3x3 mm QFN package. 1 dB compression point: +34.5 dBm typ. Logic Select pin to invert logic control The PE42552 is manufactured on Peregrines UltraCMOS High ESD: 1000 V HBM process, a patented variation of silicon-on-insulator (SOI) Absorptive switch design technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Standard 3x3 mm QFN package Figure 1. Functional Diagram RFC Figure 2. Package Type 16-lead 3x3 mm QFN RF1 RF2 ESD ESD 50 50 CMOS Control Driver LS CTRL Table 1. Target Electrical Specifications Temp = 25C, V = 3.3V, V = 0V / -3.3V DD SS Parameter Conditions Min Typical Max Units Operation Frequency MHz 9 kHz 7.5 GHz 9 KHz 0.6 0.7 dB 3000 MHz 0.65 0.8 dB Insertion Loss 6000 MHz 0.85 1.0 dB 7500 MHz 1.0 1.22 dB 3000 MHz 45 47 dB Isolation RF1 to RF2 6000 MHz 32 34 dB 7500 MHz 25 28 dB 3000 MHz 44 47 dB Isolation RFC to RFX 6000 MHz 49 55 dB 7500 MHz 37 44 dB 3000 MHz 20 dB Return Loss 6000 MHz 25 dB 7500 MHz 15 dB 50% CTRL to 0.05 dB final value (-40 to +85 C) Rising Edge 9 11 s Settling Time 50% CTRL to 0.05 dB final value (-40 to +85 C) Falling Edge 15 45 s Switching Time 50% CTRL to 90% or 10% of final value (-40 to +85 C) 5 7 s 800 MHz 32 34.5 dBm Input 1 dB Compression 7500 MHz 34 dBm Input IP3 7500 MHz 65 dBm Input IP2 7500 MHz 100 dBm Document No. 70-0246-03 www.psemi.com 2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE42552 Product Specification Figure 3. Pin Configuration (Top View) Table 4. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V Power supply voltage -0.3 4.0 V DD Voltage on any input except for V + DD V -0.3 V I CTRL and LS inputs 0.3 1 GND 12 GND V Voltage on CTRL input 4.0 V CTRL V Voltage on LS input 4.0 V RF1 2 11 LS RF2 T Storage temperature range -65 150 C ST GND 3 10 GND Input Power: P 9 kHz 1 MHz fig. 4,5 dBm GND 4 9 IN GND 1 MHz 7.5 GHz 30 dBm 1 ESD voltage (HBM) 1000 V V ESD ESD voltage (Machine Model) 100 V Note: 1. Human Body Model (HBM, MIL STD 883 Method 3015.7) Exceeding absolute maximum ratings may cause Table 2. Pin Descriptions permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation Pin No. Pin Name Description between operating range maximum and absolute 2 RF1 RF Port 1 maximum for extended periods may reduce reliability. 1, 3, 4, 5, 6, GND Ground 8, 9, 10, 12 Electrostatic Discharge (ESD) Precautions 7 RFC RF Common 11 RF2 RF Port 2 When handling this UltraCMOS device, observe the Negative supply voltage or GND same precautions that you would use with other ESD- 13 V SS connection (Note 1) sensitive devices. Although this device contains 14 CTRL CMOS level: circuitry to protect it from damage due to ESD, Logic Select - Used to determine precautions should be taken to avoid exceeding the 15 LS the definition for the CTRL pin (see rating specified. Table 5) 16 V Nominal 3.3 V supply connection DD Latch-Up Avoidance Note: 1. Use VSS (pin 13, VSS = -VDD) to bypass and disable Unlike conventional CMOS devices, UltraCMOS internal negative voltage generator. Connect VSS (pin 13) to GND devices are immune to latch-up. (VSS = 0V) to enable internal negative voltage generator. Table 5. Control Logic Truth Table Table 3. Operating Ranges LS CTRL RFC-RF1 RFC-RF2 Parameter Min Typ Max Units 0 0 off on V Positive Power Supply Voltage 3.0 3.3 3.6 V DD 0 1 on off V Negative Power Supply Voltage 1 0 on off SS -3.6 -3.3 -3.0 V (external power supply used) 1 1 off on V Negative Power Supply Voltage SS -0.1 0.0 0.0 V (internal power supply used) Logic Select (LS) I Power Supply Current DD The Logic Select feature is used to determine the 15 120 A (V = 0V, Temp = +85 C) SS definition for the CTRL pin. I Negative Supply SS -10 -40 A (V = -V , Temp = 25 C) SS DD Spurious Performance Control Voltage High 0.7xV V DD The typical spurious performance of the PE42552 is Control Voltage Low 0.3xV V DD -116 dBm when VSS=0V (pin 13 = GND). If further T Operating temperature range -40 25 85 C OP improvement is desired, the internal negative voltage 1 RF Power In (P ): IN generator can be disabled by setting VSS = -VDD. 9 kHz 1 MHz fig. 4,5 dBm 1 MHz 7.5 GHz 30 dBm Switching Frequency Note: 1. Please consult low frequency graphs on page 3 for The PE42552 has a maximum 25 kHz switching rate recommended operating power level. when the internal negative voltage generator is used (pin 13=GND). The rate at which the PE42552 can be Moisture Sensitivity Level switched is only limited to the switching time (Table 1) if The Moisture Sensitivity Level rating for the PE42552 in an external negative supply is provided at the 16-lead 3x3mm QFN package is MSL1. (pin13=VSS). 2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 UltraCMOS RFIC Solutions Page 2 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: