128K X 36 71V25761S 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features 3.3V core power supply 128K x 36 memory configuration Power down controlled by ZZ input Supports high system speed: 2.5V I/O Commercial and Industrial: Packaged in a JEDEC Standard 100-pin plastic thin quad 200MHz 3.1ns clock access time flatpack (TQFP) 183MHz 3.3ns clock access time Industrial temperature range (40C to +85C) is available for 166MHz 3.5ns clock access time selected speeds LBO input selects interleaved or linear burst mode Green parts available, see Ordering Information Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CEN Sequence 128K x 36 CLK 2 Burst 17/18 Binary BIT Logic Counter ADSC A0* MEMORY Q0 CLR ARRAY A1* Q1 ADSP 2 CLK EN A0,A1 A2 - A17 ADDRESS A0 - A16/17 36 REGISTER 36 17/18 GW Byte 1 BWE Write Register Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 OUTPUT REGISTER CE Q D CS0 Enable DATA CS1 Register INPUT CLK EN REGISTER ZZ Powerdown DQ Enable Delay Register OE OUTPUT BUFFER OE , 36 I/O0 I/O31 I/OP1 I/OP4 5297 drw 01 1 Jul.27. 2071V25761 128K x 36, 3.3V Synchronous SRAMs with 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Description cycle before it is available on the next rising clock edge. If burst mode The IDT71V25761 are high-speed SRAMs organized as 128K x 36. operation is selected (ADV=LOW), the subsequent three cycles of output The IDT71V25761 SRAMs contain write, data, address and control data will be available to the user on the next three rising clock edges. The registers. Internal logic allows the SRAM to generate a self-timed write order of these three addresses are defined by the internal burst counter based upon a decision which can be left until the end of the write cycle. and the LBO input pin. The burst mode feature offers the highest level of performance to the The IDT71V25761 SRAMs utilizes a high-performance CMOS pro- system designer, as the IDT71V25761 can provide four cycles of data for cess and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin a single address presented to the SRAM. An internal burst address plastic quad flatpack (TQFP). counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous OE Global Write Enable Input Synchronous GW Byte Write Enable Input Synchronous BWE (1) Individual Byte Write Selects Input Synchronous 1, BW2, BW3, BW4 BW CLK Clock Input N/A Burst Address Advance Input Synchronous ADV Address Status (Cache Controller) Input Synchronous ADSC Address Status (Processor) Input Synchronous ADSP Linear / Interleaved Burst Order Input DC LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5297 tbl 01 6.422 Jul.27. 20