SYNCHRONOUS ETHERNET Product Brief 82V3391 WAN PLL and Clock Generation for IEEE-1588 Provides IN3~IN14 input clocks whose frequencies cover from 2 FEATURES kHz to 625 MHz HIGHLIGHTS Includes 25MHz, 125 MHz and 156.25 MHz for CMOS inputs Single chip PLL: Includes 25MHz, 156.25 MHz, 312.5 MHz and 625 MHz for dif- Features 0.5 mHz to 560 Hz bandwidth ferential inputs Provides node clock for ITU-T G.8261/G.8262 Synchronous Internal DCO can be controlled by an external processor to be used Ethernet (SyncE) for IEEE-1588 clock generation Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) Supports Forced or Automatic operating mode switch controlled by jitter generation requirements an internal state machine. Automatic mode switch supports Free- Provides node clocks for Cellular and WLL base-station (GSM Run, Locked and Holdover modes and 3G networks) Supports manual and automatic selected input clock switch Provides clocks for DSL access concentrators (DSLAM), espe- Supports automatic hitless selected input clock switch on clock fail- cially for Japan TCM-ISDN network timing based ADSL equip- ure ments Supports three types of input clock sources: recovered clock from Provides clocks for 1 Gigabit and 10 Gigabit Ethernet application STM-N or OC-n, PDH network synchronization timing and external Supports clock generation for IEEE-1588 applications synchronization reference timing Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 MAIN FEATURES kHz or 8 kHz frame sync output signal Provides an integrated single-chip solution for Synchronous Equip- Provides a 1PPS sync Input signal, and a 1PPS sync output signal ment Timing Source, including Stratum 3, Stratum 4E, Stratum 4, Provides output clocks for BITS, GPS, 3G, GSM, etc. SMC, EEC-Option 1 and EEC-Option 2 Clocks Supports AMI, PECL/LVDS and CMOS input/output technologies Supports 1PPS input and output Supports master clock calibration Employs PLL architecture to feature excellent jitter performance Supports Master/Slave application (two chips used together) to and minimize the number of external components enable system protection against single chip failure Integrates T4 DPLL and T0 DPLL T4 DPLL locks independently or Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, locks to T0 DPLL ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom- Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 mendations steps) and damping factor (1.2 to 20 in 5 steps) -5 -8 OTHER FEATURES Supports 1.1X10 ppm absolute holdover accuracy and 4.4X10 Multiple microprocessor interface modes: EPROM, Multiplexed, ppm instantaneous holdover accuracy Intel, Motorola, I2C and Serial Supports hitless reference switching to minimize phase transients IEEE 1149.1 JTAG Boundary Scan on T0 DPLL output to be no more than 0.61 ns Single 3.3 V operation with 5 V tolerant CMOS I/Os Supports programmable input-to-output phase offset adjustment 100-pin TQFP package, green package options available Limits the phase and frequency offset of the outputs Provides OUT1~OUT7 output clocks whose frequency cover from APPLICATIONS 1PPS to 644.53125 MHz 1 Gigabit Ethernet and 10 Gigabit Ethernet Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS outputs BITS / SSU Includes 25.78125 MHz, 128.90625 MHz and 161.1328125 MHz SMC / SEC (SONET / SDH) for CMOS outputs DWDM cross-connect and transmission equipment Includes 25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625 Synchronous Ethernet equipment MHz for differential outputs Central Office Timing Source and Distribution Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, Core and access IP switches / routers 322.265625 MHz and 644.53125 MHz for differential outputs Gigabit and Terabit IP switches / routers Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/ IP and ATM core switches and access equipment 2.048 MHz (BITS/SSU) Cellular and WLL base-station node clocks Provides IN1 and IN2 for composite clocks Broadband and multi-service access equipment IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 March 5, 2012 2012 Integrated Device Technology, Inc. DSC-7238/-IDT82V3391 PRODUCT BRIEF SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588 DESCRIPTION The IDT82V3391 is an integrated, single-chip solution for the Syn- acquired in Locked mode. Whatever the operating mode is, the DPLL chronous Equipment Timing Source for Stratum 3, Stratum 4E, Stratum gives a stable performance without being affected by operating condi- 4, SMC, EEC-Option1, EEC-Option2 clocks in SONET / SDH / Synchro- tions or silicon process variations. nous Ethernet equipment, DWDM and Wireless base station. There are 2 high performance APLLs that can be used for low jitter The device supports several types of input clock sources: recovered SONET and Ethernet Clocks clock from Synchronous Ethernet, STM-N or OC-n, PDH network syn- The device provides programmable DPLL bandwidths: 0.5 mHz to chronization timing and external synchronization reference timing. 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different The device consists of T0 and T4 paths. The T0 path is a high quality settings cover all SONET / SDH clock synchronization requirements. and highly configurable path to provide system clock for node timing A highly stable input is required for the master clock in different appli- synchronization within a SONET / SDH / Synchronous Ethernet network. cations. The master clock is used as a reference clock for all the internal The T4 path is simpler and less configurable for equipment synchroniza- circuits in the device. It can be calibrated within 741 ppm. tion. The T4 path locks independently from the T0 path or locks to the T0 All the read/write registers are accessed through a microprocessor path. interface. The device supports six microprocessor interface modes: An input clock is automatically or manually selected for T0 and T4 EPROM, Multiplexed, Intel, Motorola, I2C and Serial. path. Both the T0 and T4 paths support three primary operating modes: In general, the device can be used in Master/Slave application. In Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to this application, two devices should be used together to enable system the master clock. In Locked mode, the DPLL locks to the selected input protection against single chip failure. clock. In Holdover mode, the DPLL resorts to the frequency data Description 2 March 5, 2012